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140 MHz to 1000 MHz
Quadrature Modulator
AD8345
FEATURES
140 MHz to 1000 MHz operating frequency
+2.5 dBm P1dB @ 800 MHz
−155 dBm/Hz noise floor
0.5 degree RMS phase error (IS95)
0.2 dB amplitude balance
Single 2.7 V to 5.5 V supply
Pin-compatible with AD8346 and AD8349
16-lead TSSOP_EP package
FUNCTIONAL BLOCK DIAGRAM
IBBP
1
IBBN
2
COM3
3
COM1
4
LOIN
5
LOIP
6
PHASE
SPLITTER
AD8345
16
15
14
QBBP
QBBN
COM3
COM3
VPS2
VOUT
COM2
COM3
00932-001
+
13
12
11
10
APPLICATIONS
Cellular communication systems
W-CDMA/CDMA/GSM/PCS/ISM transceivers
Fixed broadband access systems LMDS/MMDS
Wireless LAN
Wireless local loop
Digital TV/CATV modulators
Single sideband upconverter
VPS1
7
ENBL
8
BIAS
9
Figure 1.
PRODUCT DESCRIPTION
The AD8345 is a silicon RFIC quadrature modulator, designed
for use from 140 MHz to 1000 MHz. Its excellent phase
accuracy and amplitude balance enable the high performance
direct modulation of an IF carrier.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase splitter
network. The I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50 Ω drive at VOUT.
APPLICATIONS
The AD8345 modulator can be used as the IF transmit
modulator in digital communication systems such as GSM and
PCS transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz
communication systems as well as digital TV and CATV
systems.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 modulator is supplied in a 16-lead TSSOP_EP
package. Its performance is specified over a −40°C to +85°C
temperature range. This device is fabricated on Analog Devices’
advanced silicon bipolar process.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8345
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Description......................................................................... 1
Applications....................................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Equivalent Circuits ......................................................................... 10
Circuit Description......................................................................... 11
Overview...................................................................................... 11
LO Interface................................................................................. 11
Differential Voltage-to-Current Converter............................. 11
Mixers .......................................................................................... 11
Differential-to-Single-Ended Converter ................................. 11
Bias ............................................................................................... 11
Basic Connections .......................................................................... 12
LO Drive ...................................................................................... 12
LO Frequency Range ................................................................. 12
Baseband I and Q Channel Drive ............................................ 13
Reduction of LO Leakage.......................................................... 13
Single-Ended I and Q Drive...................................................... 13
RF Output.................................................................................... 14
Application with TxDAC® ......................................................... 14
Soldering Information ............................................................... 15
Evaluation Board ........................................................................ 15
Characterization Setups................................................................. 17
SSB Setup..................................................................................... 17
Modulated Waveform Setup ..................................................... 18
CDMA IS95................................................................................. 18
WCDMA 3GPP .......................................................................... 18
GSM ............................................................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
12/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 19
4/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Part Name .........................................................Universal
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/01—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8345
SPECIFICATIONS
V
S
= 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V ±0.3 V on each side for a 1.2 V p-p
differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
RF OUTPUT
Operating Frequency
1
Output Power
Min
140
0.5
0.5
−1
2.5
−155
0.5
0.2
−41
−40
−42
−33
−48
−42
−52
−60
25
59
−20
Typ
Max
1000
Unit
MHz
dBm
dBm
dBm
dBm
dBm/Hz
Degree rms
dB
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dB
Test Conditions/Comments
−3
Output P1dB
Noise Floor
Quadrature Error
I/Q Amplitude Balance
LO Leakage
+2
140 MHz
220 MHz
800 MHz
20 MHz offset from LO, all BB inputs at 0.7 V
CDMA IS95 setup (see Figure 38)
CDMA IS95 setup (see Figure 38)
140 MHz
220 MHz
800 MHz
140 MHz
220 MHz
800 MHz
−33
−40
−34
Sideband Rejection
Third Order Distortion
Second Order Distortion
Equivalent Output IP3
Equivalent Output IP2
Output Return Loss (S22)
RESPONSE TO CDMA IS95
BASEBAND SIGNALS
ACPR
EVM
Rho
LO INPUT
LO Drive level
LOIP Input Return Loss (S11)
2
See Figure 38
−72
1.3
0.9995
−10
−2
−5
−9
0
dBc
%
dBm
dB
dB
μA
pF
V
MHz
μs
μs
V
V
No termination on LOIP, LOIN at ac ground
50 Ω terminating resistor, differential drive via balun
BASEBAND INPUTS
Input Bias Current
Input Capacitance
DC Common Level
Bandwidth (3 dB)
ENABLE
Turn-On
Turn-Off
ENBL High Threshold (Logic 1)
ENBL Low Threshold (Logic 0)
POWER SUPPLIES
Voltage
Current Active
Current Standby
1
2
0.6
10
2
0.7
80
2.5
1.5
+V
S
/2
+V
S
/2
0.8
Full power (0.7 V ±0.3 V on each input, see Figure 4)
Enable high to output within 0.5 dB of final value
Enable low to supply current dropping below 2 mA
2.7
50
65
70
5.5
78
V
mA
μA
For information on operation below 140 MHz, see Figure 29.
See the LO Interface section for more details on input matching.
Rev. B | Page 3 of 20
AD8345
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPS1, VPS2
Input Power LOIP, LOIN (re 50 Ω)
IBBP, IBBN, QBBP, QBBN
Internal Power Dissipation
θ
JA
(Exposed Paddle Soldered Down)
θ
JA
(Exposed Paddle not Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
5.5 V
10 dBm
0 V, 2.5 V
500 mW
30°C/W
95°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. B | Page 4 of 20
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