FMXMC3S2106HEE-12.000000M-TR datasheet, PDF

Datasheet> All Categories > Passive components> Crystal/resonator> FMXMC3S2106HEE-12.000000M-TR

FMXMC3S2106HEE-12.000000M-TR: DescriptionParallel - Fundamental Quartz Crystal, 12MHz Nom, SMD, 2 PIN; CategoryPassive components Crystal/resonator; File Size338KB，1 Pages; ManufacturerFrequency Management International; Environmental Compliance

Download Datasheet Parametric View All

FMXMC3S2106HEE-12.000000M-TR Overview

Parallel - Fundamental Quartz Crystal, 12MHz Nom, SMD, 2 PIN

FMXMC3S2106HEE-12.000000M-TR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Frequency Management International
package instruction	SMD, 2 PIN
Reach Compliance Code	compliant
Other features	TR
Ageing	5 PPM/YEAR
Crystal/Resonator Type	PARALLEL - FUNDAMENTAL
Drive level	10 µW
frequency stability	0.0015%
frequency tolerance	30 ppm
load capacitance	6 pF
Installation features	SURFACE MOUNT
Nominal operating frequency	12 MHz
Maximum operating temperature	60 °C
Minimum operating temperature	-10 °C
physical size	5mm X 3.2mm X0.9mm
Series resistance	80 Ω
surface mount	YES
Base Number Matches	1

Preview

Download Datasheet

View All

FMXMC3S2

SERIES

Microprocessor Crystals

Surface Mount Ceramic Pkg.

Micro 5 x 3.2, 2-Pad / Ultra Thin

High Reliability

Tight Stability

Actual Size

CERAMIC SMD 5x3.2

SPECIFICATIONS

Issue 3 - 08212015

Parameter

Frequency Range

Operation Mode

Load Capacitance (CL)

Frequency Tolerance

Temperature Tolerance

Operating Temperature

Storage Temperature

Equivalent Series Resistance (ESR)

Shunt Capacitance (C0)

Drive Level

Aging @ 25°C

Insulation Resistance

Reflow Conditions

All specifications subject to change without notice.

Specification

8.00 - 150.00 MHz

See Operation Mode and ESR Table

18 pF Std., 6 - 60 pF and Series available

±30 ppm @ 25°C Std. (See Cal. Tol. for Options)

±50 ppm Std. (See Temp. Tol. for Options)

0 to +70°C Std. (See Temp. Range for Options)

-40 to +85°C / -55 to +125°C

See Operation Mode and ESR Table

7 pF max.

10 µW typical, 300 µW max

±5 ppm per year max.

500MΩ min. at 100V

±15V

260°C ±10°C for 10sec max., 2 reflows max.

5 x 3.2 CERAMIC SMD

OPERATION MODE AND ESR TABLE

Frequency (MHz)

8.00 - 10.00

10.01 - 12.00

12.01 - 20.00

20.01 - 50.00

40.00 - 150.00

Mode

Fundamental

3rd Overtone

Max. ESR (Ohms)

100

STANDARD MARKING

XXX.XXXM

FMI YYWW

XXX.XXXM FREQUENCY in MHz

FMI, Date Code

Recommended Solder Pad Layout

NOTE: Standard Specifications for product indicated in

color

Dimensions: millimeters

PART DESCRIPTION SYSTEM

FMXM C3S2 1 18 H J A

XX.XXXXXXM

Product Family

MicroP Crystal

Package

Ceramic SMD

3.2x5 mm, 2 Pad

Mode

1 - Fundamental

3 - 3rd Overtone

Load Cap. (CL)

18 - Standard (pF)

00 - Series

XX - Custom (pF)

Cal. Tol. @ 25°C

D ±10 ppm

E ±15 ppm

F ±20 ppm

H ±30 ppm

J ±50 ppm

K ±100 ppm

X Custom

Temp. Tol.

D ±10 ppm

E ±15 ppm

F ±20 ppm

H ±30 ppm

J ±50 ppm

K ±100 ppm

X Custom

Frequency (MHz)

Temp. Range

A 0 to 70 °C

B -20 to 70 °C

C -40 to 85 °C

D -10 to 50 °C

E -10 to 60 °C

F -30 to 60 °C

J 0 to 50 °C

X Custom

Options

TR - Tape & Reel

PD - Parameter Data

TD - Temp. Data

CM- Custom Mark

BLANK - None Req’d.

1-800-800-XTAL

[9825]

www.fmi-inc.com

Recommended Resources

Electric vehicle electrical schematic diagram

Simple second pulse source circuit 2

Temperature frequency converter circuit diagram

High-precision and high-stability +10V integrated regulated power supply

Chunhua brand vacuum cleaner electronic speed control circuit

Computer motherboard circuit diagram 820 1_67

Is the reset of the DDR3 chip on the HPS side always low?: I made a board myself, the reset pin of the DDR3 chip on the HPS side is always low, but the DE1 development board does not have any program burned inside, and the pin is high level when powered on. I...; hellboy158 FPGA/CPLD

The difference between arm dsp and fpga: [b] The difference between arm, dsp and fpga[/b] Huangyuan Mange 08-05-28 16:36 Published at: [url=http://www.xici.net/b804866/board.asp][color=#0000ff]《EmbeddedWay Embedded System》[/color][/url] Cate...; 安_然 DSP and ARM Processors

How about studying FPGA for mechanical graduate students?: [font=微软雅黑][size=7]I am a graduate student now. My teacher has no projects. I want to learn FPGA by myself. I would like to ask Da Sheng to help me plan. How far can I reach in two years? I feel that ...; tao147258 FPGA/CPLD

【labview】: Data manipulation routines in loops...; 安_然 Test/Measurement

What path planning algorithms are generally used by GPS navigators?: RT. Is it Dijkstra? But the complexity of O(n^2) is too high for a city, and the chip of a GPS navigation system cannot bear it. Or is it some approximate algorithm?...; rogergui Embedded System

PX2 shares Android preset desktop customization and power icon modification and version changes: Currently, the desktop uses Google Launcher2 by default. The source code location is: sdk/packages/apps/Launcher2. The desktop shortcut is modified in: sdk/packages/apps/Launcher2/res/xml/default_work...; 穿prada的008 Linux and Android

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components