3D3323
MONOLITHIC TRIPLE
FIXED DELAY LINE
(SERIES 3D3323)
FEATURES
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All-silicon, low-power CMOS technology
Vapor phase, IR and wave solderable
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
10 through 6000ns
Delay tolerance:
2% or 1.0ns
Temperature stability:
±3%
typ (-40C to 85C)
Vdd stability:
±1%
typical (3.0V to 3.6V)
Minimum input pulse width:
20% of total delay
PACKAGES
I1
I2
I3
GND
1
2
3
4
8
7
6
5
VDD
O1
O2
O3
3D3323Z SOIC
(150 Mil)
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
The 3D3323 Triple Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains three matched,
independent delay lines. Delay values can range from 10ns through
6000ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D3323
is CMOS-compatible and features both rising- and falling-edge
accuracy.
The all-CMOS 3D3323 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered
in a space saving surface mount 8-pin SOIC.
PIN DESCRIPTIONS
I1
I2
I3
O1
O2
O3
VDD
GND
N/C
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
+3.3 Volts
Ground
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DELAY
PER LINE
(ns)
10
±
1.0
15
±
1.0
20
±
1.0
25
±
1.0
30
±
1.0
40
±
1.0
50
±
1.0
100
±
2.0
200
±
4.0
500
±
10.0
1000
±
20
2000
±
40
5000
±100
6000
±120
Max Operating
Frequency
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
0.67 MHz
0.33 MHz
0.17 MHz
0.07 MHz
0.05 MHz
INPUT RESTRICTIONS
Absolute Max
Min Operating
Oper. Freq.
Pulse Width
100.0 MHz
15.0 ns
100.0 MHz
22.5 ns
100.0 MHz
30.0 ns
83.3 MHz
37.5 ns
71.4 MHz
45.0 ns
62.5 MHz
60.0 ns
50.0 MHz
75.0 ns
25.0 MHz
150.0 ns
12.5 MHz
300.0 ns
5.00 MHz
750.0 ns
2.50 MHz
1500.0 ns
1.25 MHz
3000.0 ns
0.50 MHz
7500.0 ns
0.42 MHz
9000.0 ns
Absolute Min
Oper. P.W.
5.0 ns
5.0 ns
5.0 ns
6.0 ns
7.0 ns
8.0 ns
10.0 ns
20.0 ns
40.0 ns
100.0 ns
200.0 ns
400.0 ns
1000.0 ns
1200.0 ns
3D3323Z-10
3D3323Z -15
3D3323Z -20
3D3323Z -25
3D3323Z -30
3D3323Z -40
3D3323Z -50
3D3323Z -100
3D3323Z -200
3D3323Z -500
3D3323Z -1000
3D3323Z -2000
3D3323Z -5000
3D3323Z -6000
NOTE:
Any delay between 10 and 6000 ns not shown is also available.
2007
Data Delay Devices
Doc #06017
6/25/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3323
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3323 triple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
To guarantee the
Table 1
delay accuracy for
input frequencies higher than the
Maximum
Operating Frequency,
the 3D3323 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification,
the part number will include a
custom reference designator
identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a
Maximum
and
an
Absolute Maximum
operating input
frequency and a
Minimum
and an
Absolute
Minimum
operating pulse width have been
specified.
OPERATING PULSE WIDTH
The
Absolute Minimum Operating Pulse
Width
(high or low) specification, tabulated in
Table 1,
determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The
Minimum Operating Pulse Width
(high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in
Table 1
is
guaranteed.
To guarantee the
Table 1
delay accuracy for
input pulse width smaller than the
Minimum
Operating Pulse Width,
the 3D3323 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the
part number will include a
O1
O2
O3
OPERATING FREQUENCY
The
Absolute Maximum Operating Frequency
specification, tabulated in
Table 1,
determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The
Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
VDD
Temp & VDD
Compensation
Delay
Line
Delay
Line
Delay
Line
GND
I1
I2
I3
Figure 1: 3D3323 Functional Diagram
Doc #06017
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D3323
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
300
PPM/C,
which is equivalent to a variation , over
the -40C to 85C operating range, of
±3%
from
the room-temperature delay settings and/or
1.0ns,
whichever is greater. The
power supply
coefficient
is reduced, over the 3.0V to 3.6V
operating range, to
±1%
of the delay settings at
the nominal 3.3VDC power supply and/or
2.0ns,
whichever is greater.
It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3323 programmable delay line
utilizes novel and innovative compensation
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
-1
-1
0.8
1
1
-4.0
MAX
5
UNITS
mA
V
V
µA
µA
mA
mA
2
ns
NOTES
4.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 3 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #06017
6/25/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D3323
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
3.3V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW
IN
= 1.25 x Total Delay
Period:
PER
IN
= 2.5 x Total Delay
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
1.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
REF
PULSE
GENERATOR
OUT
TRIG
IN1 DEVICE UNDER
TEST (DUT)
IN2
IN3
OUT1
OUT2
OUT3
IN
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
PER
IN
PW
IN
t
RISE
INPUT
SIGNAL
2.4V
1.5V
0.6V
t
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
t
PHL
t
PLH
OUTPUT
SIGNAL
1.5V
V
OH
1.5V
V
OL
Figure 3: Timing Diagram
Doc #06017
6/25/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
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