DS1004Z-3T datasheet, PDF - EEWORLD Datasheet

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DS1004Z-3T: DescriptionSilicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, MINI, SOIC-8; Categorylogic logic; File Size54KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1004Z-3T Overview

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, MINI, SOIC-8

DS1004Z-3T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
package instruction	SOP,
Reach Compliance Code	compliant
Other features	INPUT TO 1ST TAP DELAY = 5NS
series	CMOS/TTL
Input frequency maximum value (fmax)	36.7647 MHz
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	1
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	17 ns
width	3.9 mm
Base Number Matches	1

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DS1004

5-Tap High Speed

Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon timing circuit

Five delayed clock phases per input

Precise tap-to-tap nominal delay tolerances of

±0.75 and ±1 ns

Input-to-tap 1 delay of 5 ns

Nominal Delay tolerances of ±1.5 ns

Leading and trailing edge precision preserves

the input symmetry

CMOS design with TTL compatibility

Standard 8-pin DIP and 150 mil 8-pin SOIC

Vapor phase, IR and wave solderable

Available in Tape and Reel

PIN ASSIGNMENT

TAP 2

TAP 4

GND

TAP 1

TAP 3

TAP 5

DS1004M 8-Pin DIP (300-mil)

See Mech. Drawings Section

TAP 2

TAP 4

GND

TAP 1

TAP 3

TAP 5

DS1004Z 8-Pin SOIC (150-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-5

GND

- TAP Output Number

- +5V Supply

- Ground

- Input

DESCRIPTION

The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a

standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a

standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge

accuracies and has the inherent reliability of an all-silicon delay line solution.

The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum

input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns.

See Table 1 for details. Input to Tap Tolerance over temperature and voltage is

±1.5

ns in addition to the

nominal delay tolerance. Nominal tap-to-tap tolerances range from

±0.75

ns to

±1.0

ns. Each output is

capable of driving up to 10 LS loads.

For customers needing non-standard delay values, the Late Package Program (LPP) is available.

Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.

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092500

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