54ACT109MW8 datasheet, PDF - EEWORLD Datasheet

54ACT109MW8: DescriptionACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16; Categorylogic logic; File Size181KB，8 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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54ACT109MW8 Overview

ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16

Parameter Name	Attribute value
Maker	Texas Instruments
package instruction	DIE,
Reach Compliance Code	unknown
series	ACT
JESD-30 code	X-XUUC-N16
Logic integrated circuit type	J-KBAR FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	UNSPECIFIED
Package form	UNCASED CHIP
propagation delay (tpd)	12 ns
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal location	UPPER
Trigger type	POSITIVE EDGE
minfmax	85 MHz
Base Number Matches	1

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