19-1166; Rev 0; 12/96
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________General Description
The MAX1101 is a highly integrated IC designed pri-
marily for digitizing the output of a linear CCD array. It
provides the components required for all necessary
analog functions, including clamp circuitry for black-
level correction or correlated double sampling (CDS), a
three-input multiplexer (mux), and an 8-bit analog-to-
digital converter (ADC).
The MAX1101 operates with a sample rate up to 1MHz
and with a wide range of linear CCDs. The logic inter-
face is serial, and a single input sets the bidirectional
data line as either data in or data out, thus minimizing
the I/O pins required for communication.
Packaged in a 24-pin SO, the MAX1101 is available in
the commercial (0°C to +70°C) temperature range.
____________________________Features
o
1.0 Million Pixels/sec Conversion Rate
o
Built-In Clamp Circuitry for Black-Level
Correction or Correlated Double Sampling
o
64-Step PGA, Programmable from Gain = -2 to -10
o
Auxiliary Mux Inputs for Added Versatility
o
Compatible with a Large Range of CCDs
o
8-Bit ADC Included
o
Space-Saving, 24-Pin SO Package
MAX1101
________________________Applications
Scanners
Fax Machines
Digital Copiers
CCD Imaging
______________Ordering Information
PART
MAX1101CWG
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
24 Wide SO
Pin Configuration appears on last page.
___________________________________________________Typical Operating Circuit
C
EXT
0.047µF
1
2
3
GND
CCDIN
GND
AIN1
GND
AIN2
GND
GND
24
23
22
21
20
19
18
17
16
µP/µC/
STATE LOGIC
0.1µF
+5V DC (SUPPLY)
MAX1101
V
DD
CLAMP
CCD
ARRAY
4
5
6
7
VIDSAMP
LOAD
DATA
SCLK
MODE
GND
V
DD
15
11
0.1µF
1 2
AUXILIARY
ANALOG INPUTS
12
REFGND
REF-
REFBIAS
REF+
14
13
0.1µF
+5V DC (REFERENCE)
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
MAX1101
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ............................................................-0.3V to +12V
All Pins to GND...........................................-0.3V to (V
DD
+ 0.3V)
Current into Every Pin (except V
DD
) .................................±20mA
Current into V
DD
...............................................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
SO (derate 11.76mW/°C above +70°C) ......................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= V
REFBIAS
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C
EXT
= 47nF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
PARAMETER
Resolution
Differential Nonlinearity
Integral Nonlinearity
Total Unadjusted Error
Zero-Scale Drift
Full-Scale Drift
Maximum Sample Rate
Minimum Sample Rate
Input Full-Power Bandwidth
Aperture Delay
ANALOG INPUT—CCD INTERFACE
Maximum Peak CCD
Differential Signal Range
Minimum PGA Gain Setting
Maximum PGA Gain Setting
Gain Adjust Resolution
Gain Adjust Step Size
PGA Gain Error
Black Sample Switch On-Resistance R
ON(BSS)
Input Leakage (Note 2)
CCD Interface Offset Voltage
I
L(CCDIN)
V
OS(CCD)
Including black sample switch off-leakage
V
VIDEO
= V
RESET
(Figure 4)
0
V
WHITE
V
WHITE
=
(V
REF+
- V
REF-
) / G
PGA
G
PGA
= -2
G
PGA
= -10
-1.9
-9.375
1.25
0.25
-2
-9.875
64
0.125
±5
60
1
4
150
50
8
-2.1
-10.375
V
V/V
V/V
Steps
V/V
% Gain
Ω
nA
LSB
t
AP
SYMBOL
N
DNL
INL
TUE
TCVOS
TCFS
f
s
(Note 1)
V
IN
= 2.5Vp-p
0.67
1
1
10
125
0.016
1.2
No-missing-codes guaranteed
Best straight-line fit
CONDITIONS
MIN
8
±0.5
±1
±1
±1.5
±2.5
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
%µV/°C
%FS/°C
MHz
kHz
MHz
ns
ANALOG-TO-DIGITAL CONVERTER
ANALOG INPUT—AUXILIARY INPUTS
Input Voltage Range
Input Capacitance (Note 1)
On-Resistance
V
IN
C
IN(ON)
C
IN(OFF)
R
ON
Channel on
Channel off
120
V
REF-
V
REF+
45
10
V
pF
Ω
2
_______________________________________________________________________________________
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
REFBIAS
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C
EXT
= 47nF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
PARAMETER
REFERENCE VOLTAGE INPUT
Positive Reference Voltage
Negative Reference Voltage
POWER SUPPLIES
Positive Supply-Voltage Range
PSRR, PGA and ADC
Supply Current
DIGITAL INPUTS/OUTPUTS
Digital Input Voltage High
Digital Input Voltage Low
Digital Input Leakage Current
Digital Output Voltage High
Digital Output Voltage Low
Digital Output Leakage Current
SCLK Frequency
SCLK Pulse Width
VIDSAMP Pulse Width
VIDSAMP to CLAMP Separation
LOAD Pulse Width
VIDSAMP Fall to SCLK Rise Time
VIDSAMP Fall to DATA
VIDSAMP to Reset Separation
Reset to CLAMP Separation
SCLK Rise to DATA
DATA Set-Up Time
DATA Hold Time
LOAD Fall to SCLK Rise Time
SCLK Rise to LOAD Rise Time
MODE Setup Time
CLAMP Pulse Width
CLAMP Fall to Video Update
Digital Quiet Time (Note 3)
V
IH
V
IL
I
IL
V
OH
V
OL
I
OL
f
SCLK
t
SPW
t
VS
t
VB
t
LD
t
VLS
t
VLD
t
VR
t
RB
t
SD
t
DSU
t
DH
t
LS
t
SL
t
MSU
t
BS
t
BC
t
Q
(Note 1)
± around VIDSAMP falling edge
MODE = 0
MODE = 0
Same as bus-relinquish time
20
20
50
50
50
300
20
20
MODE = 1
MODE = 1
(Note 2)
(Note 2)
50
50
60
50
500
50
50
50
60
I
SOURCE
= 4mA
I
SINK
= 4mA
Output in high-impedance mode
-10
-10
V
DD
- 0.5
0.5
10
10
3.5
1.5
10
V
V
µA
V
V
µA
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
DD
PSRR
I
DD
4.75V
≤
V
DD
≤
5.25V
4.75
48
5
60
20
40
5.25
V
dB
mA
V
REF+
V
REF-
Internally generated, V
REFBIAS
= 5V
Internally generated, V
REFBIAS
= 5V
2.94
0.49
3.00
0.50
3.06
0.51
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1101
DIGITAL TIMING SPECIFICATIONS
(t
r
, t
f
≤
10ns, C
L
≤
50pF, unless otherwise noted)
Note 1:
Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as
performance may degrade, particularly at high temperatures.
Note 2:
Production test equipment settling time prohibits leakage measurements below 1nA.
Lab equipment has shown the MAX1101 switch input leakage below 1pA at T
A
= +25°C, and below 50pA at T
A
= +70°C.
Note 3:
Not a test parameter. Recommended for optimal performance.
_______________________________________________________________________________________
3
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
MAX1101
______________________________________________________________Pin Description
PIN
1, 3, 5, 7,
10, 16, 24
2
4
6
8, 9, 10
11
12
13
14
15, 23
17
18
19
20
21
22
NAME
GND
CCDIN
AIN1
AIN2
I.C.
REFGND
REF-
REF+
REFBIAS
V
DD
MODE
SCLK
DATA
LOAD
VIDSAMP
CLAMP
Ground
CCD Input. Connect CCD through a series 0.047µF capacitor (C
EXT
).
Auxiliary Analog Input Channel 1
Auxiliary Analog Input Channel 2
Internally Connected. Do not connect to this pin.
Reference Ground. Ground reference for all analog signals.
Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND
≤
REF-
≤
REF+.
Nominally 0.5V.
Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF-
≤
REF+
≤
V
DD
.
Nominally 3.0V.
Reference Power Supply. Connect to external +5.0V to set V
REF+
to +3.0V and V
REF-
to +0.5V.
Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together,
close to the MAX1101.
Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the
PGA and mux.
Serial Clock Input
Data Input or Output, as controlled by MODE
Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0.
Control Input. Samples the video level and initiates the ADC conversion.
Control Input. Samples black level. Can be used for correlated double sampling.
FUNCTION
REFBIAS
AIN2
AIN1
2
1
MUX
CCDIN
CLAMP
CLAMP
CIRCUIT
PGA
GAIN
6
0
2
ADC
8
REF-
_______________Detailed Description
Overview
The MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
and noise errors through an internal clamp circuit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
REF+
REFGND
VIDSAMP
REGISTER
6
REGISTER
2
REGISTER
8
DATA
SCLK
LOAD
MODE
SERIAL
PORT
Figure 1. MAX1101 Functional Diagram
4
_______________________________________________________________________________________
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
MAX1101
REF+
REF+
REF-
S1
CF
CLAMP
S1
S1P
FROM
CCD
C
EXT
0.047µF
S2
C
I
TO
ADC
REF-
REF-
VIDSAMP
S1
*
S2
*
S1P
*
ON
OFF
OFF
ON
OFF
ON
* INTERNALLY GENERATED SIGNALS
V
REF
+
- V
VIDEO
(FROM DC
RESTORE)
C
I
V
OUT
= V
REF
- ±V
0S
S2
C
I
C
F
REF+
REF-
Figure 3a. PGA Connection with VIDSAMP = Low
C
F
REF-
Figure 2. PGA Functional Diagram
Figure 3b. PGA Connection with VIDSAMP = High
Programmable-Gain Amplifier
The PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier’s
gain is set by the ratio C
I
/C
F
. The input is sampled on
the C
I
capacitors, which is a set of equal capacitors.
The 6-bit gain control word determines the number
of capacitors used. Thus the PGA gain is set from
-2 to -10.
A voltage equal to V
REF-
is applied to the PGA’s nonin-
verting input. This offsets the PGA output to be within
the range of the ADC (V
REF-
to V
REF+
).
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier’s
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier’s offset voltage has been stored on these
capacitors and is thus canceled. The amplifier’s output
is [C
F
/C
I
] x V
VIDEO
+ V
REF-
. The CDS function is shown
in Figure 4.
ADC
The ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors, the flash ADC compares the unknown input
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
5
Clamp Circuit
As shown in Figure 2, the CCD output is connected to
the MAX1101 input (CCDIN) through an external
capacitor, which removes the potentially large DC
common-mode voltages from the input signal.
Whenever CLAMP is high, the CLAMP switch is closed
and C
EXT
is charged to V
REF+
. It can be actuated
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
_______________________________________________________________________________________
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