Threshold voltage, transformer Coupled, Measured on
Stub (Note 7)
Common-Mode Voltage (Note 8)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35 Ohm,
Measured on bus
Transformer Coupled Across 70 Ohm,
Measured on Stub (Note 9)
Output Noise, differential (Direct coupled)
Output Offset Voltage, transformer Coupled Across 70 Ohm
Rise/Fall Time
LOGIC
V
IH
V
IL
I
IH
(TXIN, TXIN, TXINHIBIT, SLEEP)
I
IH
(STROBE)
I
IL
(TXIN, TXIN, TXINHIBIT, SLEEP)
I
IL
(STROBE)
V
OH
(I
OH
=max)
V
OL
(I
OL
=min)
I
OL
I
OH
POWER SUPPLY REQUIREMENTS
Voltages/Tolerance
+3.3V
Current Drain (Note 10)
• SLEEP asserted
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
POWER DISSIPATION, V
CC
= +3.3V (NOTE 10)
• SLEEP asserted
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
THERMAL
Thermal Resistance, Junction-to-Heatsink
Thermal Resistance, Junction-to-Board (Note 11)
Heat sink soldered to PC board (2s2p - JESD51-5)
Operating Case Bottom Temperature
Operating Junction Temperature
Storage Temperature
Pad Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Moisture Sensitivity Level
Package Body Size
32-pad LPCC
Weight
7
14
-55
-55
-65
MIN
TYP
MAX
UNITS
-0.3
20
0.200
3.3
4.5
Vdc
kOhm
pF
Vp-p
Vpeak
50
0.860
10
6
20
-250
100
0.7 x Vcc
20
0
-100
Vcc - 0.4
2.0
7.2
21.5
9
27
10
250
300
Vp-p
Vp-p
mVp-p
mVp
ns
V
V
µA
µA
µA
µA
V
V
mA
mA
150
0.3 x Vcc
100
0
-20
0.4
-2.0
3.15
3.3
3.45
6
33
225
417
800
0.02
0.11
0.43
0.75
1.40
9
17
+125
+150
+150
+300
V
mA
mA
mA
mA
mA
W
W
W
W
W
°C/W
°C/W
°C
°C
°C
°C
—
in.
(mm)
oz
(g)
MSL-2
0.280 X 0.280 X 0.040
(7.1 x 7.1 x 1.0)
0.0049
(0.14)
Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (assumed tied together externally without a transformer).
(2) Impedance parameters are specified directly between pads Tx Data Out/RX Data In and Tx Data Out / RX Data In of the package.
(3) It is assumed that all power and ground inputs to the package are connected.
(4) The specifications are applicable for both un-powered and powered conditions.
(5) The specifications assume a 1.5-volt rms balanced differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz.
Data Device Corporation
www.ddc-web.com
3
BU-63133L8
Rev G-6/10-0
TABLE 1 Notes (Continued):
(6) Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested.
(7) The Threshold Level, as referred to in this specification, is meant to be the maximum peak-to-peak voltage (measured on the stub) that can be
applied to the receiver's input without causing the output to change from the OFF state.
(8) Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to pins of the isolation transformer on the stub side (either
direct or transformer coupled), and referenced to hybrid ground. Transformer must be a DDC recommended transformer.
(9) MIL-STD-1760 requires minimum output voltage of 20Vp-p on the stub connection.
(10) Current drain and power dissipation specifications are preliminary and subject to change. Power dissipation specifications assume a transformer
coupled configuration with external dissipation (while transmitting with 100% duty cycle) of 1.4W (for 1760 amplitudes), which is the power delivered
to the 1553 fault isolation resistors, the power delivered to the bus termination resistors, the copper losses in the transceiver isolation transformer
and the bus coupling transformer.
(11) Thermal resistance specs are preliminary and subject to change. Junction-to-board thermal resistance is measured in accordance with JEDEC
standard JESD51-8. The 16 thermal vias connecting the LPCC heatsink to PCB internal plane are in accordance with JEDEC JESD51-5 (2s2p).
Each via is 0.3 mm diameter with 0.035 mm plating. Please refer to JEDEC standard JESD51-5 for detailed PCB construction.
(12) To calculate the loading effect on the stub side of the "long stub" isolation transformer, multiply "R" by 7.29 (Isolation Transformer ratio of 2.70²)
and divide "C" by 7.3. For "short stub" isolation transformers, multiply "R" by 14.06 (Isolation Transformer ratio of 3.75²) and divide "C" by 14.1.
INTRODUCTION
The BU-63133L8 is a single transmitter and receiver packaged in
a 32-pad Leadless Plastic Chip Carrier (LPCC). It is directly com-
patible to the Harris 15530 encoder/decoder and has internal
(factory preset) threshold levels. The transceiver only requires
+3.3V power and conforms to MIL-STD-1553A and 1553B.
FIGURE 3 illustrates the connection between a BU-63133L8
transceiver and a MIL-STD-1553 Data Bus. After transformer
isolating the transceiver, it can be either direct coupled (short
stub) or transformer coupled (long stub) to the Data Bus.
When STROBE is high data passes through the receiver to RX
DATA OUT and RX DATA OUT. Applying a low to STROBE disables
the receiver output terminals. As illustrated in FIGURE 2, the receiv-
er in the BU-63133L8 provides compatibility to the Harris type
decoder.
WAVEFORMS
FIGURE 2 illustrates the BU-63133L8 with Harris type decoder
interface. Note that TX DATA IN and TX DATA IN inputs must be
complementary waveforms with a 50% duty cycle.
SLEEP OPERATING MODE
When the SLEEP input is asserted (logic "1"), the BU-63133L8
disables it's transmitter (both outputs go to a high impedance
state) and goes into a power saving mode. Applying a low to
STROBE then disables both receiver output terminals. If the
SLEEP function is not needed, this pad may be tied low.
1553 BUS INTERFACE AND LAYOUT
CONSIDERATIONS
FIGURE 3 illustrates the interface between the BU-63133L8 and
a MIL-STD-1553 bus. Connections for both direct (short stub)
and transformer (long stub) coupling, as well as the peak-to-
peak voltage levels at various points (when transmitting), are
indicated in the diagram.
TRANSMIT OPERATING MODE
The transmitter section accepts encoded TTL data and converts
it to bi-phase Manchester II form using a waveshaping network
and driver circuits. The driver outputs TX DATA OUT and TX
DATA OUT are transformer coupled to the Data Bus.
The transmitter output terminals can be put into a high imped-
ance state by setting TX INHIBIT high, or setting TX DATA IN and
TX DATA IN to the same logic level.
BU-63133L8
ENCODER
OUTPUT
(NOTE 2)
TX Data In
TX Data In
LINE-TO-LINE
OUTPUT
LINE-TO-LINE
INPUT
XXX
XXX
X X X
X X X
RX Data Out
RX Data Out
RECEIVER OPERATING MODE
The receiver section accepts data from a MIL-STD-1553 Data
Bus when coupled to the Data Bus as shown in FIGURE 3. This
data is converted to TTL and furnished to RX DATA OUT and RX
DATA OUT.
Data Device Corporation
www.ddc-web.com
Notes:
(1) TX Data In and RX Data Out are TTL signals.
(2) TX Data In inputs must be at the same logic level when not transmitting.
(3) LINE-TO-LINE output voltage is measured between TX Data Out and TX Data Out.
(4) LINE-TO-LINE input voltage is measured on the Data Bus.
FIGURE 2. WAVEFORMS FOR HARRIS TYPE
ENCODER/DECODER
BU-63133L8
Rev G-6/10-0
4
Note that the BU-63133L8 has multiple pads for each of the TX
DATA OUT phases. All pads of the same signal phase must be
connected together on the PCB to assure adequate current car-
rying capacity.
The center tap of the primary winding (the side of the trans-
former that connects to the BU-63133L8) must be directly con-
nected to the +3.3V plane. Additionally, a 10µF low inductance
tantalum capacitor and 0.01µF ceramic capacitor must be
mounted as close as possible and with the shortest leads to the
center tap of the transformer(s) and ground plane.
Furthermore, when transmitting, large currents will flow from the
3.3V plane, into the transformer center tap, through the primaries,
into the TX pads and then out through the transceiver ground pads
into the ground plane. The traces in this path should be sized
accordingly and the connections to the ground plane should be as
short as possible. Note that the heatsink on the bottom of the pack-
age is also electrically grounded.
It is recommended that the BU-63133L8 be bypassed with a
1.0µF low inductance tantalum capacitor in parallel with a 0.01µF
ceramic capacitor. These capacitors should be located as close
to the Vcc and GND pads as possible.
To achieve its full military temperature range rating, the
BU-63133L8 needs to be properly heat sinked. The thermal
resistance junction-to-board specification (TABLE 1) allows for
16 thermal vias connecting the heatsink on the package bottom
to a 2s2p (2 sided, 2 plane PCB), 3.0" x 4.5". The thermal via
construction follows JEDEC standard JESD51-5 with thermal
vias connecting the top side mini-plane located under the heat-
sink to the upper internal plane. The board temperature is deter-
mined 1mm from the package in accordance with JEDEC stan-
dard JESD51-8.
The 2s2p PCB construction has 2 inner planes of 1 oz copper, 2
outer trace layers of 2 oz copper and has an overall thickness of 1.6
mm, which is divided evenly amongst the 3 dielectrics. The top layer
has 8 traces (0.26 mm width each) fanning out from each side of the
package. Refer to the appropriate JEDEC standards, and DDC’s
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