MP7616
15 V CMOS
16-Bit Multiplying
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
Monolithic CMOS Construction
Full Four-Quadrant Multiplication
Excellent Stability Over Temperature and Time
TTL/5 V CMOS Compatible
Guaranteed Monotonic
•
•
•
•
Low Sensitivity to Output Amplifier Vos
Low Glitch Energy
Buffered Version: MP7626
5 V Version: MP7616B
GENERAL DESCRIPTION
The MP7616 is a high density 16-bit CMOS multiplying Digi-
tal-to-Analog Converter. Silicon nitride passivation and un-
trimmed silicon chromium resistors have been combined to pro-
vide long term stability and reliability. Using the most significant
bit (MSB) segmentation technique, the MP7616 features 13-bit
(0.012%) differential and 12-bit (0.01%) integral linearity.
To achieve 13-bit linearity without laser trim, the MP7616 digi-
tally decodes the four MSB’s into 15 equal current sources,
rather than the standard binary-weighted sources. Each resis-
tor contributes only 1/16 full scale output thus reducing the
matching accuracy requirement of the resistor and CMOS
switches from 0.0015% to 0.024%.
The decoding technique achieves an eightfold improvement
in differential linearity stability over temperature, an eightfold im-
provement in relative accuracy due to aging effects (long term
stability), a fourfold improvement in glitch amplitude, and a ten-
fold reduction in sensitivity to output amplifier offset voltage.
SIMPLIFIED BLOCK DIAGRAM
V
DD
V
REF
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
12-Bit
DAC
I
OUT2
I
OUT1
To Switches
To 12-Bit DAC
R
FB
4 to 15 Decoder
1
MSB
4
5
16
LSB
GND
Rev. 2.00
1
MP7616
ORDERING INFORMATION
Package
Type
Plastic Dip
Plastic Dip
SOIC
SOIC
Ceramic Dip
Ceramic Dip
Ceramic Dip
Temperature
Range
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–55 to +125
°
C
Part No.
MP7616JN
MP7616KN
MP7616JS
MP7616KS
MP7616JD
MP7616KD
MP7616TD*
INL
(LSB)
+14
+7
+14
+7
+14
+7
+7
DNL
(LSB)
+16
+8
+16
+8
+16
+8
+8
Gain Error
(% FSR)
+0.8
+0.8
+0.8
+0.8
+0.8
+0.8
+0.8
*Contact factory for non-compliant military processing
PIN CONFIGURATION
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
1
2
3
4
5
6
7
8
9
10
11
See Packaging Section for Package Dimensions
N/C
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
22
21
20
19
18
17
16
15
14
13
12
BIT 2
BIT 1 (MSB)
GND
I
OUT2
I
OUT1
R
FB
V
REF
V
DD
BIT 16 (LSB)
BIT 15
BIT 14
BIT 2
BIT 1 (MSB)
GND
I
OUT2
I
OUT1
R
FB
V
REF
V
DD
BIT 16 (LSB)
BIT 15
BIT 14
N/C
22 Pin CDIP, PDIP (0.400”)
D22, N22
24 Pin SOIC (Jedec, 0.300”)
S24
PIN OUT DEFINITIONS
DIP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
NAME
N/C
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
DESCRIPTION
No Connection
Data Input Bit 3
Data Input Bit 4
Data Input Bit 5
Data Input Bit 6
Data Input Bit 7
Data Input Bit 8
Data Input Bit 9
Data Input Bit 10
Data Input Bit 11
Data Input Bit 12
Data Input Bit 13
DIP
SOIC
13
14
15
16
17
18
19
20
21
22
23
24
NAME
N/C
BIT 14
BIT 15
BIT 16
V
DD
V
REF
R
FB
I
OUT1
I
OUT2
GND
BIT 1
BIT 2
DESCRIPTION
No Connection
Data Input Bit 14
Data Input Bit 15
Data Input Bit 16 (LSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
Current Output 1
Current Output 2
Ground
Data Input Bit 1 (MSB)
Data Input Bit 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Rev. 2.00
2
MP7616
ELECTRICAL CHARACTERISTICS
(V
DD
= + 15 V, V
REF
= +10 V unless otherwise noted)
25
°
C
Typ
Tmin to Tmax
Min
Max
Parameter
STATIC PERFORMANCE
1
Resolution (All Grades)
Integral Non-Linearity
5
(Relative Accuracy)
J
K, T
Differential Non-Linearity
5
J
K, T
Gain Error
Gain Temperature Coefficient
2
Non-Linearity Tempco
2
Differential Linearity Tempco
2
Power Supply Rejection Ratio
Output Leakage Current
6
DYNAMIC PERFORMANCE
2
Current Settling Time
Feedthrough at I
OUT1
REFERENCE INPUT
Input Resistance
DIGITAL INPUTS
3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
ANALOG OUTPUTS
2
Output Capacitance
Symbol
Min
Max
Units
Test Conditions/Comments
FSR = Full Scale Range
N
INL
16
16
Bits
LSB
Best Fit Straight Line Spec.
(Max INL – Min INL) / 2
+14
+7
DNL
+16
+8
GE
TC
GE
+0.8
+14
+7
LSB
+16
+8
% FSR
+2.0
+0.5
+0.5
ppm/°C
ppm/°C
ppm/°C
ppm/%
nA
|∆Gain/∆V
DD
| ∆V
DD
= + 5%
Using Internal R
FB
∆Gain/∆Temperature
PSRR
I
OUT
+5
+1
+50
+10
+50
+200
t
S
F
T
2
1
2
µs
mV p-p
To 0.01% of FSR; all digital inputs
low to high and high to low
V
REF
= 10kHz, 20 Vp-p
R
IN
1
3
10
1
10
kΩ
V
IH
V
IL
I
LKG
3.0
2.4
0.8
+1.0
3.0
0.8
+1.0
V
V
µA
C
OUT1
C
OUT1
C
OUT2
C
OUT2
POWER SUPPLY
4
Functional Voltage Range
2
Supply Current
V
DD
I
DD
4.5
100
50
50
100
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
15
0.4
16
4
4.5
16
4
V
mA
All digital inputs = 0 V or all = 5 V
Rev. 2.00
3
MP7616
ELECTRICAL CHARACTERISTICS (CONT’D)
NOTES:
1
Full Scale Range (FSR) is 10V for unipolar mode.
2
Guaranteed but not production tested.
3
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
Specified values guarantee functionality. Refer to other parameters for accuracy.
5
Linearity error is degraded by 65µV for every mV of voltage offset at output amplifier.
6
Output leakage current refers to I
OUT1
. One LSB of current constantly flows into I
OUT2
(30nA at 5kΩ input impedance,
V
REF
= +10 V) due to ladder termination into I
OUT2
.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V
Digital Input Voltage to GND . . . . GND –0.5 to V
DD
+0.5 V
I
OUT1
, I
OUT2
to GND . . . . . . . . . . . GND –0.5 to V
DD
+0.5 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
V
RFB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
Storage Temperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300
°
C
Package Power Dissipation Rating to 75
°
C
CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . 1000mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . 13mW/
°
C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
APPLICATION NOTES
Refer to Section 8 for Applications Information
Rev. 2.00
4
MP7616
22 LEAD CERAMIC DUAL-IN-LINE
(400 MIL CDIP)
D22
S
1
22
S
12
See
Note 1
1
11
E
1
D
Base
Plane
Seating
Plane
L
e
b
b
1
c
L
1
Q
A
E
α
INCHES
SYMBOL
A
b
b
1
c
D
E
E
1
e
L
L
1
Q
S
S
1
MIN
––
0.014
0.038
0.008
––
0.350
0.390
MAX
.225
0.023
0.065
0.015
1.111
0.410
0.420
MILLIMETERS
MIN
––
0.356
0.965
0.203
––
8.89
9.91
MAX
5.72
0.584
1.65
0.381
28.22
10.41
10.67
NOTES
––
––
2
––
4
4
7
5
––
––
3
6
6
––
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one and is within the
shaded area shown.
2. The minimum limit for dimension b
1
may be 0.023
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating
plane to the base plane.
4. This dimension allows for off-center lid, meniscus and
glass overrun.
5. The basic lead spacing is 0.100 inch (2.54 mm) be-
tween centerlines.
6. Applies to all four corners.
7. This is measured to outside of lead, not center.
0.100 BSC
0.125
0.150
0.015
––
0.005
0
°
0.200
––
0.070
0.080
––
15
°
2.54 BSC
3.18
3.81
0.381
––
0.13
0
°
5.08
––
1.78
2.03
––
15
°
α
Rev. 2.00
5
Embedded System
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