54ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and
TRI-STATE Outputs
September 1998
54ACTQ657
Quiet Series Octal Bidirectional Transceiver with 8-Bit
Parity Generator/Checker and TRI-STATE
®
Outputs
General Description
The ACTQ657 contains eight non-inverting buffers with
TRI-STATE outputs and an 8-bit parity generator/checker. In-
tended for bus oriented applications, the device combines
the ’245 and the ’280 functions in one package.
The ACTQ utilizes NSC Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO
™
output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Combines the ’245 and the ’280 functions in one
package
n
Outputs source/sink 24 mA
n
’ACTQ has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD)
5962-92197
Logic Symbols
IEEE/IEC
DS100244-1
DS100244-4
GTO
™
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100244
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100244-3
DS100244-2
Pin Names
A
0
–A
7
B
0
–B
7
T/R
OE
PARITY
ODD/EVEN
ERROR
Description
Data Inputs/TRI-STATE Outputs
Data Inputs/TRI-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/TRI-STATE Output
ODD/EVEN Parity Input
Error TRI-STATE Output
www.national.com
2
Functional Description
The Transmit/Receive (T/R) input determines the direction of
the data flow through the bidirectional transceivers. Transmit
(active HIGH) enables data from the A port to the B port; Re-
ceive (active LOW) enables data from the B port to the A
port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B ports by placing them
in a HIGH-Z condition when the Output Enable input is
HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A port are
HIGH and compares these with the condition of the parity se-
lect (ODD/EVEN). If the Parity Select is HIGH and an even
number of A inputs are HIGH, the Parity output is HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B port are HIGH, the parity select
is HIGH, and the PARITY input is HIGH, the ERROR will be
LOW indicating an error.
3
www.national.com
Functional Description
Function Table
Number of
Inputs That
Are High
0, 2, 4, 6, 8
OE
L
L
L
L
L
L
1, 3, 5, 7
L
L
L
L
L
L
Immaterial
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
(Continued)
Inputs
T/R
H
H
L
L
L
L
H
H
L
L
L
L
X
ODD/EVEN
H
L
H
H
L
L
H
L
H
H
L
L
X
Input/
Output
Parity
H
L
H
L
H
L
L
H
H
L
H
L
Z
ERROR
Z
Z
H
L
L
H
Z
Z
L
H
H
L
Z
Outputs
Outputs Mode
Transmit
Transmit
Receive
Receive
Receive
Receive
Transmit
Transmit
Receive
Receive
Receive
Receive
Z
H
Function Table
Inputs
OE
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Outputs
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
High-Z State
www.national.com
4
Functional Block Diagram
DS100244-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
www.national.com
京公网安备 11010802033920号
EEWORLD
