M80C86 M80C86-2
16-BIT CHMOS MICROPROCESSOR
MILITARY
Y
Pin-for-Pin and Functionally Compatible
to Industry Standard HMOS M8086
Fully Static Design with Frequency
Range from D C to
5 MHz for M80C86
8 MHz for M80C86-2
Low Power Operation
Operating I
CC
e
10 mA MHz
Standby I
CCS
e
500
mA
max
Bus-Hold Circuitry Eliminates Pull-Up
Resistors
Direct Addressing Capability of
1 MByte of Memory
Y
Y
Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
24 Operand Addressing Modes
Byte Word and Block Operations
8 and 16-Bit Signed and Unsigned
Arithmetic
Binary or Decimal
Multiply and Divide
Military Temperature Range
b
55 C to
a
125 C (T
C
)
Y
Y
Y
Y
Y
Y
Y
The Intel M80C86 is a high performance CHMOS version of the industry standard HMOS M8086 16-bit CPU It
is available in 5 and 8 MHz clock rates The M80C86 offers two modes of operation MINimum for small
systems and MAXimum for larger applications such as multiprocessing It is available in 40-pin DIP package
271058 –1
271058 –2
Figure 1 M80C86 CPU Block Diagram
Figure 2 M80C86 40-Lead DIP Configuration
November 1989
Order Number 271058-005
M80C86 M80C86-2
Table 1 Pin Description
The following pin function descriptions are for M80C86 systems in either minimum or maximum mode The
‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the M80C86 (without
regard to additional bus buffers)
Symbol
AD
15
–AD
0
Pin No
2 – 16 39
Type
I O
Name and Function
ADDRESS DATA BUS
These lines constitute the time multiplexed
memory IO address (T
1
) and data (T
2
T
3
T
W
T
4
) bus A
0
is
analogous to BHE for the lower byte of the data bus pins D
7
– D
0
It
is LOW during T
1
when a byte is to be transferred on the lower
portion of the bus in memory or I O operations Eight-bit oriented
devices tied to the lower half would normally use A
0
to condition
chip select functions (See BHE ) These lines are active HIGH and
float to 3-state OFF
(1)
during interrupt acknowledge and local bus
‘‘hold acknowledge ’’
ADDRESS STATUS
During T
1
these are the four most significant
address lines for memory operations During I O operations
these lines are LOW During memory and I O operations
status information is available on these lines during T
2
T
3
T
W
and T
4
The status of the interrupt enable FLAG bit (S
5
) is updated
at the beginning of each CLK cycle A
17
S
4
and A
16
S
3
are
encoded as shown
This information indicates which relocation register is presently
being used for data accessing
These lines float to 3-state OFF
(1)
during local bus ‘‘hold
acknowledge ’’
A
17
S
4
0 (LOW)
0
1 (HIGH)
1
S
6
is 0
(LOW)
BHE S
7
34
O
A
16
S
3
0
1
0
1
Characteristics
Alternate Data
Stack
Code or None
Data
A
19
A
18
A
17
A
16
S
6
S
5
S
4
S
3
35– 38
O
BUS HIGH ENABLE STATUS
During T
1
the bus high enable signal
(BHE) should be used to enable data onto the most significant half
of the data bus pins D
15
–D
8
Eight-bit oriented devices tied to the
upper half of the bus would normally use BHE to condition chip
select functions BHE is LOW during T
1
for read write and interrupt
acknowledge cycles when a byte is to be transferred on the high
portion of the bus The S
7
status information is available during T
2
T
3
and T
4
The signal is active LOW and floats to 3-state OFF
(1)
in
‘‘hold ’’ It is LOW during T
1
for the first interrupt acknowledge cycle
BHE
0
0
1
1
A
0
0
1
0
1
Characteristics
Whole word
Upper byte from
to odd address
Lower byte from
to even address
None
2
M80C86 M80C86-2
Table 1 Pin Description
(Continued)
Symbol
RD
Pin No
32
Type
O
Name and Function
READ
Read strobe indicates that the processor is performing a
memory of I O read cycle depending on the state of the S
2
pin
This signal is used to read devices which reside on the M80C86
local bus RD is active LOW during T
2
T
3
and T
W
of any read cycle
and is guaranteed to remain HIGH in T
2
until the M80C86 local bus
has floated
This floats to 3-state OFF in ‘‘hold acknowledge ’’
READY
22
I
READY
is the acknowledgement from the addressed memory or
I O device that it will complete the data transfer The READY signal
from memory IO is synchronized by the M82C84A Clock Generator
to form READY This signal is active HIGH The M80C86 READY
input is not synchronized Correct operation is not guaranteed if the
setup and hold times are not met
INTERRUPT REQUEST
is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation A
subroutine is vectored to via an interrupt vector lookup table
located in system memory It can be internally masked by software
resetting the interrupt enable bit INTR is internally synchronized
This signal is active HIGH
TEST
input is examined by the ‘‘Wait’’ instruction If the TEST input
is LOW execution continues otherwise the processor waits in an
‘‘Idle’’ state This input is synchronized internally during each clock
cycle on the leading edge of CLK
NON-MASKABLE INTERRUPT
an edge triggered input which
causes a type 2 interrupt A subroutine is vectored to via an
interrupt vector lookup table located in system memory NMI is not
maskable internally by software A transition from a LOW to HIGH
initiates the interrupt at the end of the current instruction This input
is internally synchronized
RESET
causes the processor to immediately terminate its present
activity The signal must be active HIGH for at least four clock
cycles It restarts execution as described in the Instruction Set
description when RESET returns LOW RESET is internally
synchronized
CLOCK
provides the basic timing for the processor and bus
controller It is asymmetric with a 33% duty cycle to provide
optimized internal timing
V
CC
a
5V power supply pin
GROUND
Both must be connected
I
MINIMUM MAXIMUM
indicates what mode the processor is to
operate in The two modes are discussed in the following sections
INTR
18
I
TEST
23
I
NMI
17
I
RESET
21
I
CLK
19
I
V
CC
GND
MN MX
40
1 20
33
3
M80C86 M80C86-2
Table 1 Pin Description
(Continued)
The following pin function descriptions are for the M80C86 M82C88 system in maximum mode (i e
MN MX
e
V
SS
) Only the pin functions which are unique to maximum mode are described all other pin func-
tions are as described above
Symbol
S
2
S
1
S
0
Pin No
26 – 28
Type
O
Name and Function
STATUS
active during T
4
T
1
and T
2
and is returned to the passive
state (1 1 1) during T
3
or during T
W
when READY is HIGH This
status is used by the M82C88 Bus Controller to generate all memory
and I O access control signals Any change by S
2
S
1
S
0
during T
4
is used to indicate the beginning of a bus cycle and the return to the
passive state in T
3
or T
W
is used to indicate the end of a bus cycle
These signals float to 3-state OFF
(1)
in ‘‘hold acknowledge ’’ These
status lines are encoded as shown
S
2
0 (LOW)
0
0
0
1 (HIGH)
1
1
1
RQ GT
0
RQ GT
1
30 31
I O
S
1
0
0
1
1
0
0
1
1
S
0
0
1
0
1
0
1
0
1
Characteristics
Interrupt
Acknowledge
Read I O Port
Write I O Port
Halt
Code Access
Read Memory
Write Memory
Passive
REQUEST GRANT
pins are used by other local bus masters to
force the processor to release the local bus at the end of the
processor’s current bus cycle Each pin is bidirectional with RQ GT
0
having higher priority than RQ GT
1
RQ GT has an internal pull-up
resistor so may be left unconnected The request grant sequence is
as follows (see timing diagram)
1 A pulse of 1 CLK wide from another local bus master indicates a
local bus request (‘‘hold’’) to the M80C86 (pulse 1)
2 During a T
4
or T
1
clock cycle a pulse 1 CLK wide from the
M80C86 to the requesting master (pulse 2) indicates that the
M80C86 has allowed the local bus to float and that it will enter the
‘‘hold acknowledge’’ state at the next CLK The CPU’s bus interface
unit is disconnected logically from the local bus during ‘‘hold
acknowledge ’’
3 A pulse 1 CLK wide from the requesting master indicates to the
M80C86 (pulse 3) that the ‘‘hold’’ request is about to end and that
M80C86 can reclaim the local bus at the next CLK
Each master-master exchange of the local bus is a sequence of 3
pulses There must be one dead CLK cycle after each bus exchange
Pulses are active LOW
If the request is made while the CPU is performing a memory cycle it
will release the local bus during T
4
of the cycle when all the following
conditions are met
1 Request occurs on or before T
2
2 Current cycle is not the low byte of a word (on an odd address)
3 Current cycle is not the first acknowledge of an interrupt
acknowledge sequence
4 A locked instruction is not currently executing
4
M80C86 M80C86-2
Table 1 Pin Description
(Continued)
Symbol
Pin No
Type
Name and Function
If the local bus is idle when the request is made the two possible
events will follow
1 Local bus will be released during the next clock
2 A memory cycle will start within 3 clocks Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied
LOCK
29
O
LOCK
output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK
signal is activated by the ‘‘LOCK’’ prefix instruction and remains
active until the completion of the next instruction This signal is active
LOW and floats to 3-state OFF
(1)
in ‘‘hold acknowledge ’’
QUEUE STATUS
The queue status is valid during the CLK cycle
after which the queue operation is performed
QS
1
and QS
0
provide status to allow external tracking of the internal
M80C86 instruction queue
QS
1
0 (LOW)
0
1 (HIGH)
1
QS
0
0
1
0
1
Characteristics
No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue
QS
1
QS
0
24 25
O
The following pin function descriptions are for the M80C86 in minimum mode (i e MN MX
e
V
CC
) Only the
pin functions which are unique to minimum mode are described all other pin functions are described above
M IO
28
O
STATUS LINE
logically equivalent to S
2
in the maximum mode It
is used to distinguish a memory access from an I O access M IO
becomes valid in the T
4
preceding a bus cycle and remains valid
until the final T
4
of the cycle (M
e
HIGH IO
e
LOW) M IO floats to
3-state OFF
(1)
in local bus ‘‘hold acknowledge ’’
WRITE
indicates that the processor is performing a write memory
or write I O cycle depending on the state of the M IO signal WR is
active for T
2
T
3
and T
W
of any write cycle It is active LOW and
floats to 3-state OFF
(1)
in local bus ‘‘hold acknowledge ’’
INTA is used as a read strobe for interrupt acknowledge cycles It is
active LOW during T
2
T
3
and T
W
of each interrupt acknowledge
cycle
ADDRESS LATCH ENABLE
provided by the processor to latch
the address into an address latch It is a HIGH pulse active during
T
1
of any bus cycle Note that ALE is never floated
DATA TRANSMIT RECEIVE
needed in minimum system that
desires to use a data bus transceiver It is used to control the
direction of data flow through the transceiver Logically DT R is
equivalent to S
1
in the maximum mode and its timing is the same
as for M IO (T
e
HIGH R
e
LOW ) This signal floats to 3-state
OFF
(1)
in local bus ‘‘hold acknowledge ’’
WR
29
O
INTA
24
O
ALE
25
O
DT R
27
O
5
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