QL5332-33APB256I datasheet, PDF

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QL5332-33APB256I: DescriptionBus Controller, CMOS, PBGA256,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size361KB，18 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL5332-33APB256I Overview

Bus Controller, CMOS, PBGA256,

QL5332-33APB256I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
Humidity sensitivity level	3
Number of terminals	256
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA256,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	3.3,3.3/5 V
Certification status	Not Qualified
Maximum slew rate	2 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Base Number Matches	1

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QL5332 - Enhanced QuickPCI

Device

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

last updated 2/5/01

QL5332 - Enhanced QL5032

PCI Bus – 33 MHz 32 bits (data and address)

Supports all PCI commands (including configuration

and MWI)

Supports fully-customizable byte enables as a master

Zero-wait-state write and one-wait-state read target

interface

Supports all types of PCI target terminations: disconnect

with data transfer, disconnect without data transfer,

and retry

Supports target aborts

Has 125 more logic cells in FPGA section, but 2 less

RAM blocks

Pin Compatible with QL5032

PCI CONTROLLER

MASTER

CONTROLLER

HIGH

SPEED

DATA

PATH

TARGET

CONTROLLER

INTERFACE

154 User I/O

160

MHz

FIFOs

High Speed

Logic Cells

Config

Space

DMA

Controller

PROGRAMMABLE LOGIC

Device Highlights

High Performance PCI Controller

FIGURE 1. QL5332 Diagram

Extendable PCI Functionality

32-bit / 33 MHz PCI Master/Target

Zero-wait state PCI Master provides 132 MB/s

transfer rates

Zero-wait-state PCI Target Write/One-wait-state PCI

Target Read interface

Supports all PCI commands, including configuration

and MWI

Supports fully-customizable byte enable for master

channels

Target interface supports retry, disconnect with/without

data transfer, and target abort

Programmable back-end interface to optional local

processor

Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

Fully customizable PCI Configuration Space

Configurable FIFOs with depths up to 256

Reference design with driver code (Win 95/98/

Win 2000/NT4.0) available

PCI v2.2 compliant

Supports Type 0 Configuration Cycles in Target mode

3.3V, 5V Tolerant PCI signaling supports Universal

PCI Adapter designs

3.3V CMOS in 208-pin PQFP and 256-pin PBGA

Supports endian conversions

Unlimited/Continuous Burst Transfers supported

Support for PCI host-bridge function

Support for Configuration Space from 0x40 to 0x3FF

Multi-Function, Expanded Capabilities, & Expansion

ROM capable

Power management, Compact PCI, hot-swap/

hot-plug compatible

PCI v2.2 Power Management Spec compatible

PCI v2.2 Vital Product Data (VPD) configuration support

Programmable Interrupt Generator

O support with local processor

Mailbox register support

Programmable Logic

515 Logic Cells

13,824 RAM bits, up to 154 I/O pins

250 MHz 16-bit counters, 275 MHz Datapaths,

160 MHz FIFOs

All back-end interface and glue-logic can be implemented

on chip

Any combination of FIFOs that require 12 or less

QuickLogic RAM Modules

Six 32-bit busses interface between the PCI Controller and

the Programmable Logic

Rev B

QL5332 - QuickPCI

PCI Master Interface

The internal signals used to interface with the PCI controller in the QL5332 are listed below, along with a description

of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or an output pro-

vided by the PCI controller (o). Signals that end with the character ‘N’ should be considered active-low (for example,

Mst_IRDYN

PCI_Cmd[3:0]

PCI command to be used for the master transaction. This signal must remain unchanged throughout the period

when Mst_Burst_Req is active. PCI commands considered as reads include Interrupt Acknowledge, I/O Read,

Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as

writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate.

Users should make sure that only valid PCI commands are supplied.

Request use of the PCI bus. When it is active, the core requests the PCI bus and then generates a master trans-

action. This signal should be held active until all requested data are transferred on the PCI bus and deactivated

in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new

transaction).

Address for master DMA writes. This address must be treated as valid from the beginning of a DMA write until

the DMA write operation is complete. It should be incremented (by 4 bytes) each time data is transferred on

the PCI bus.

Address for master DMA reads. This address must be treated as valid from the beginning of a DMA read until

the DMA read operation is complete. It should be incremented (by 4 bytes) each time data is transferred on the

PCI bus.

Data for master DMA writes (to PCI bus).

Byte enables for master DMA reads and writes. Active-low.

Data and byte enable valid on Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both master read

and write).

Data receive acknowledge for Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both). This

serves as the PUSH control for the internal FIFO and the POP control for the external FIFO (in FPGA region)

which provides data and byte enables to the PCI32 core.

Byte enable select for master transactions. When low, Mst_BE[3:0] should remain constant throughout the

entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction.

When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of master write) is used. Should be

held constant throughout the transaction.

Master write transaction is completed. Active for only one clock cycle.

Master read termination mode select when Mst_BE_Sel is high. When both Mst_BE_Sel and

Mst_Rd_Term_Sel are high, master read termination happens when the internal FIFO is empty, and

Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads and

Mst_One_Read are used to signal end of master read. Should be held constant throughout the transaction.

This signals to the PCI32 core that only one data transfer remains to be read in the burst read.

Two data transfers remain to be read in the burst read. It is not used for single-data-phase master read

transactions.

Master read data valid on Usr_Addr_WrData[31:0]. This serves as the PUSH control for the external FIFO (in

FPGA region) that receives data from the PCI32 core.

Master read transaction is completed. Active for only one clock cycle.

Internal FIFO flush. FIFO flushed immediately after it is active (synchronized with PCI clock).

Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch).

For full PCI compliance, this port should be always set to 1.

Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read

operations.

Active during the last data transfer of a master transaction.

Copy of the PCI REQN signal generated by QL5x33 as PCI master. Not usually used in the back-end design.

Mst_Burst_Req

Mst_WrAd[31:0]

Mst_RdAd[31:0]

Mst_WrData[31:0]

Mst_BE[3:0]

Mst_WrData_Valid

Mst_WrData_Rdy

Mst_BE_Sel

Mst_WrBurst_Done

Mst_Rd_Term_Sel

Mst_One_Read

Mst_Two_Reads

Mst_RdData_Valid

Mst_RdBurst_Done

Flush_FIFO

Mst_LatCntEn

Mst_Xfer_D1

Mst_Last_Cycle

Mst_REQN

QL5332-33APB256I Related Products

	QL5332-33APB256I	QL5332-33APQ208C	QL5332-33APB256C	QL5332-33APQ208I
Description	Bus Controller, CMOS, PBGA256,	PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208	Bus Controller, CMOS, PBGA256,	Bus Controller, CMOS, PQFP208,
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation
Reach Compliance Code	compliant	compliant	compliant	compliant
JESD-30 code	S-PBGA-B256	S-PQFP-G208	S-PBGA-B256	S-PQFP-G208
JESD-609 code	e0	e0	e0	e0
Humidity sensitivity level	3	3	3	3
Number of terminals	256	208	256	208
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	FQFP	BGA	QFP
Encapsulate equivalent code	BGA256,20X20,50	QFP208,1.2SQ,20	BGA256,20X20,50	QFP208,1.2SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK, FINE PITCH	GRID ARRAY	FLATPACK
power supply	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	2 mA	2 mA	2 mA	2 mA
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	GULL WING	BALL	GULL WING
Terminal pitch	1.27 mm	0.5 mm	1.27 mm	0.5 mm
Terminal location	BOTTOM	QUAD	BOTTOM	QUAD
Base Number Matches	1	1	1	1

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