QL5332 - Enhanced QuickPCI
TM
Device
33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM
last updated 2/5/01
QL5332 - Enhanced QL5032
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PCI Bus – 33 MHz 32 bits (data and address)
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Supports all PCI commands (including configuration
and MWI)
Supports fully-customizable byte enables as a master
Zero-wait-state write and one-wait-state read target
interface
Supports all types of PCI target terminations: disconnect
with data transfer, disconnect without data transfer,
and retry
Supports target aborts
Has 125 more logic cells in FPGA section, but 2 less
RAM blocks
Pin Compatible with QL5032
PCI CONTROLLER
MASTER
CONTROLLER
HIGH
SPEED
DATA
PATH
TARGET
CONTROLLER
32
INTERFACE
154 User I/O
160
MHz
FIFOs
High Speed
Logic Cells
Config
Space
DMA
Controller
PROGRAMMABLE LOGIC
Device Highlights
High Performance PCI Controller
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FIGURE 1. QL5332 Diagram
Extendable PCI Functionality
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32-bit / 33 MHz PCI Master/Target
Zero-wait state PCI Master provides 132 MB/s
transfer rates
Zero-wait-state PCI Target Write/One-wait-state PCI
Target Read interface
Supports all PCI commands, including configuration
and MWI
Supports fully-customizable byte enable for master
channels
Target interface supports retry, disconnect with/without
data transfer, and target abort
Programmable back-end interface to optional local
processor
Independent PCI bus (33 MHz) and local bus
(up to 160 MHz) clocks
Fully customizable PCI Configuration Space
Configurable FIFOs with depths up to 256
Reference design with driver code (Win 95/98/
Win 2000/NT4.0) available
PCI v2.2 compliant
Supports Type 0 Configuration Cycles in Target mode
3.3V, 5V Tolerant PCI signaling supports Universal
PCI Adapter designs
3.3V CMOS in 208-pin PQFP and 256-pin PBGA
Supports endian conversions
Unlimited/Continuous Burst Transfers supported
Support for PCI host-bridge function
Support for Configuration Space from 0x40 to 0x3FF
Multi-Function, Expanded Capabilities, & Expansion
ROM capable
Power management, Compact PCI, hot-swap/
hot-plug compatible
PCI v2.2 Power Management Spec compatible
PCI v2.2 Vital Product Data (VPD) configuration support
Programmable Interrupt Generator
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O support with local processor
Mailbox register support
Programmable Logic
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515 Logic Cells
13,824 RAM bits, up to 154 I/O pins
250 MHz 16-bit counters, 275 MHz Datapaths,
160 MHz FIFOs
All back-end interface and glue-logic can be implemented
on chip
Any combination of FIFOs that require 12 or less
QuickLogic RAM Modules
Six 32-bit busses interface between the PCI Controller and
the Programmable Logic
Rev B
QL5332 - QuickPCI
TM
Architecture Overview
The QL5332 device in the QuickLogic QuickPCI ESP
(Embedded Standard Product) family provides a
complete and customizable PCI interface solution
combined with programmable logic. This device
eliminates any need for the designer to worry about
PCI bus compliance, yet allows for the maximum 32-
bit PCI bus bandwidth (132 MB/s).
The programmable logic portion of the device
contains 515 QuickLogic Logic Cells, and 12
QuickLogic Dual-Port RAM Blocks. These
configurable RAM blocks can be configured in many
width/depth combinations. They can also be
combined with logic cells to form FIFOs, or be
initialized via Serial EEPROM on power-up and used
as ROMs.
The QL5332 device meets PCI 2.2 electrical and
timing specifications and has been fully hardware-
tested. This device also supports the Win'98 and
PC'98 standards. The QL5332 device features 3.3-
volt operation with multi-volt compatible I/Os. Thus it
can easily operate in 3-volt systems and is fully
compatible with 3.3V, 5V or Universal PCI card
applications.
The Target interface offers full PCI Configuration
Space and flexible target addressing. It supports zero-
wait-state target write and one-wait-state target read
operations. It also supports retry, disconnect with/
without data transfer, and target abort requested by
the backend. Any number of 32-bit BARs may be con-
figured, as either memory or I/O space. All required
and optional PCI 2.2 Configuration Space registers
can be implemented within the programmable region
of the device. A reference design of a Target Configu-
ration and Addressing module is provided.
The interface ports are divided into a set of ports for
master transactions and a set for target transactions.
The Master DMA controller and Target Configuration
Space and Address Decoding are done in the pro-
grammable logic region of the device. Since these
functions are not timing critical, leaving these ele-
ments in the programmable region allows the greatest
degree of flexibility to the designer. Reference DMA
controller, Configuration Space, and Address Decod-
ing blocks are included so that the design cycle can be
minimized.
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Com-
pliant Master/Target Controller. It is capable of infi-
nite length Master Write and Read transactions at zero
wait states (132 MBytes/second). The Master will
never insert wait states during transfers, so data should
be supplied or received by FIFOs, which can be config-
ured in the programmable region of the device. The
Master is capable of initiating any type of PCI com-
mand, including configuration cycles and Memory
Write and Invalidate (MWI). This enables the QL5332
device to act as a PCI host. The Master Controller will
most often be operated by a DMA Controller in the
programmable region of the device. A DMA Control-
ler reference design is available.
Configuration Space and
Address Decode
The configuration space is completely customizable in
the programmable region of the device.
PCI address and command decoding is performed by
logic in the programmable section of the device. This
allows support for any size of memory or I/O space
for back-end logic. It also allows the user to implement
any subset of the PCI commands supported by the
QL5332. QuickLogic provides a reference Address
Register/Counter and Command Decode block.
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Preliminary
QL5332 - QuickPCI
TM
DMA Master/Target Control
The customizable DMA controller included with the
QuickWorks design software contains the following
features:
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Configurable FIFOs
FIFOs may be created with the RAM/FIFO wizard in
the QuickWorks tools. The figure below shows the
graphical interface used to create these FIFOs.
FIFOs may be designed up to 256 deep. With 12
RAM cells available in the QL5332, that allows for
up to 6 FIFOs at 64 deep (36 wide), 3 FIFOs at 128
deep (36 wide), or 1 FIFO at 256 deep (48 wide).
Configurable DMA count size for Reads and Writes
(up to 30-bits)
Configurable DMA burst size for PCI (including
unlimited/continuous burst)
Customizable PCI command to use by core
Customizable Byte Enable signal
Programmable Arbitration between DMA Read &
Write transactions
DMA Registers may be mapped to any area of
Target Memory Space
-
Read Address (32-bit register)
- Write Address (32-bit register)
- Read Length (16-bit register) / Write Length
(16-bit register)
- Control and Status (32-bit register, includes 8 bit
Burst Length)
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DMA Registers are available to the local design or
the PCI bus
Programmable Interrupt Control to signal end of
transfer or other event
FIGURE 2: Graphical Interface to create FIFO
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QL5332 - QuickPCI
TM
PCI Interface Symbol
The figure below shows the interface symbol you would use in your schematic design in order to attach the local
interface programmable logic design to the PCI core. If you were designing with a top-level Verilog or VHDL file,
then you would use a structural instantiation of this PCI32N block, instead of a graphical symbol.
FIGURE 3: PCI Interface Symbol
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4
Preliminary
QL5332 - QuickPCI
TM
PCI Master Interface
The internal signals used to interface with the PCI controller in the QL5332 are listed below, along with a description
of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or an output pro-
vided by the PCI controller (o). Signals that end with the character ‘N’ should be considered active-low (for example,
Mst_IRDYN
).
PCI_Cmd[3:0]
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PCI command to be used for the master transaction. This signal must remain unchanged throughout the period
when Mst_Burst_Req is active. PCI commands considered as reads include Interrupt Acknowledge, I/O Read,
Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as
writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate.
Users should make sure that only valid PCI commands are supplied.
Request use of the PCI bus. When it is active, the core requests the PCI bus and then generates a master trans-
action. This signal should be held active until all requested data are transferred on the PCI bus and deactivated
in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new
transaction).
Address for master DMA writes. This address must be treated as valid from the beginning of a DMA write until
the DMA write operation is complete. It should be incremented (by 4 bytes) each time data is transferred on
the PCI bus.
Address for master DMA reads. This address must be treated as valid from the beginning of a DMA read until
the DMA read operation is complete. It should be incremented (by 4 bytes) each time data is transferred on the
PCI bus.
Data for master DMA writes (to PCI bus).
Byte enables for master DMA reads and writes. Active-low.
Data and byte enable valid on Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both master read
and write).
Data receive acknowledge for Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both). This
serves as the PUSH control for the internal FIFO and the POP control for the external FIFO (in FPGA region)
which provides data and byte enables to the PCI32 core.
Byte enable select for master transactions. When low, Mst_BE[3:0] should remain constant throughout the
entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction.
When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of master write) is used. Should be
held constant throughout the transaction.
Master write transaction is completed. Active for only one clock cycle.
Master read termination mode select when Mst_BE_Sel is high. When both Mst_BE_Sel and
Mst_Rd_Term_Sel are high, master read termination happens when the internal FIFO is empty, and
Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads and
Mst_One_Read are used to signal end of master read. Should be held constant throughout the transaction.
This signals to the PCI32 core that only one data transfer remains to be read in the burst read.
Two data transfers remain to be read in the burst read. It is not used for single-data-phase master read
transactions.
Master read data valid on Usr_Addr_WrData[31:0]. This serves as the PUSH control for the external FIFO (in
FPGA region) that receives data from the PCI32 core.
Master read transaction is completed. Active for only one clock cycle.
Internal FIFO flush. FIFO flushed immediately after it is active (synchronized with PCI clock).
Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch).
For full PCI compliance, this port should be always set to 1.
Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read
operations.
Active during the last data transfer of a master transaction.
Copy of the PCI REQN signal generated by QL5x33 as PCI master. Not usually used in the back-end design.
Mst_Burst_Req
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Mst_WrAd[31:0]
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Mst_RdAd[31:0]
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Mst_WrData[31:0]
Mst_BE[3:0]
Mst_WrData_Valid
Mst_WrData_Rdy
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Mst_BE_Sel
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Mst_WrBurst_Done
Mst_Rd_Term_Sel
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Mst_One_Read
Mst_Two_Reads
Mst_RdData_Valid
Mst_RdBurst_Done
Flush_FIFO
Mst_LatCntEn
Mst_Xfer_D1
Mst_Last_Cycle
Mst_REQN
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