S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C72M5/C72M7/C72M9 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-1280-dot LCD direct drive capability, segment expandable circuit, 8-bit and 16-bit timer/counter,
and serial I/O, the S3C72M5/C72M7/C72M9 offers an excellent design solution for a wide variety of applications
which require LCD functions.
Up to 51 pins of the 128-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide fast
response to internal and external events. In addition, the S3C72M5/C72M7/C72M9's advanced CMOS
technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C72M5/C72M7/C72M9 microcontroller is also available in OTP (One Time Programmable) version,
S3P72M9. S3P72M9 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of
masked ROM. The S3P72M9 is comparable to S3C72M5/C72M7/C72M9, both in function and in pin
configuration except ROM size.
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PRODUCT OVERVIEW
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
FEATURES SUMMARY
Memory
•
3,584
×
4-bit RAM
(Excluding LCD Display
RAM)
16,384/24,576/32,768
×
8-bit ROM
16-Bit Timer/Counter
•
•
•
•
51 I/O Pins
•
•
I/O: 47 pins (32 pins are
configurable as SEG pins)
Input only: 4 pins
•
•
Programmable 16-bit timer
External event counter
Arbitrary clock frequency
output
External clock signal divider
Configurable as two 8-bit
Timers
Serial I/O interface clock
generator
Bit Sequential Carrier
•
Supports 16-bit serial data
transfer in arbitrary format
•
Memory-Mapped I/O Structure
•
Data memory bank 15
Power-Down Modes
•
•
•
Idle mode (only CPU clock
stops)
Stop mode (main system
clock stops)
Subsystem clock stop mode
LCD Controller/Driver
•
•
•
•
•
80 SEG
×
16 COM, 88 SEG
×
8 COM Terminals
Internal resistor circuit for
LCD bias
16 Level LCD contrast
control (software)
Segment expandable circuit
All dot can be switched
on/off
Watch Timer
•
•
•
Time interval generation:
0.5 s, 3.9 ms at 32,768 Hz
4 frequency outputs to BUZ
pin
Clock source generation for
LCD
Oscillation Sources
•
•
•
•
•
Crystal, Ceramic or RC for
main system clock
Crystal oscillator for
subsystem clock
Main system clock
frequency: 0.4–6 MHz
Subsystem clock frequency:
32.768 kHz
CPU clock divider circuit
(by 4, 8 or 64)
8-bit Serial I/O Interface
•
•
•
•
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first
transmission selectable
Internal or external clock
source
8-bit Basic Timer
•
•
4 interval timer functions
Watch-dog timer
Instruction Execution Times
•
•
•
0.67, 1.33, 10.7 µs at 6 MHz
0.95, 1.91, 15.3 µs at 4.19
MHz
122 µs at 32.768 kHz
8-bit Timer/Counter
•
•
•
•
Programmable 8-bit timer
External event counter
Arbitrary clock frequency
output
External clock signal divider
Comparator
•
•
3 Channel mode: internal
reference (4-bit resolution)
2 Channel mode: external
reference
Operating Temperature
•
– 40
°
C to 85
°
C
Interrupts
•
•
•
Five internal vectored
interrupts
Four external vectored
interrupts
Two quasi-interrupts
Operating Voltage Range
•
1.8 V to 5.5 V
Package Type
•
128-pin QFP
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S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 15-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instructions stored in a look-up table in the
ROM. Whenever a reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logical zero.
During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.
The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 16,384/24,576/32,768
×
8-bit ROM is divided into four areas:
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 16-byte general-purpose area (0010–001FH)
— 16,256/24,448/32,640-byte area for general-purpose program memory
The vector address area is used mostly during reset operations and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.
The REF instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020H–007FH.
REF can also reference three-byte instructions such as JP or CALL. So that a REF instruction can reference
these instructions, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is
written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused
locations in the REF instruction look-up area can be allocated to general-purpose use.
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PRODUCT OVERVIEW
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
DATA MEMORY
Overview
The 3,584-bit data memory has five areas:
— 32Ê
´ Ê
-bit working register area
Ê
4
— 224Ê
´
-bit general-purpose area in bank 0 which is also used as the stack area
4
— 256Ê
´
-bit general-purpose area in bank 1, bank 2,…, bank 13, respectively
4
…
— 256Ê
´
5-bit area for LCD data in bank 14
— 128Ê
´
4-bit area in bank 15 for memory-mapped I/O addresses
The data memory area is also organized as sixteen memory banks —
bank 0, bank 1, … and bank 15. You use
..,
the select memory bank instruction (SMB) to select one of the banks as working data memory.
Data stored in RAM locations are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, … or 15. When
..,
the EMB flag is logical zero, only locations 00H–7FH of bank 0 and bank 15 can be accessed. When the EMB
flag is set to logical one, all sixteen data memory banks can be accessed based on the current SMB value.
Working Registers
The RAM's working register area in data memory bank 0 is also divided into four
register
banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.
Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL and HL are used as address pointers for indirect addressing.
To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.
LCD Data Register Area
Bit values for LCD segment data are stored in data memory bank 14. Register locations that are not used to store
LCD data can be assigned to general-purpose use.
Bit Sequential Carrier
The bit sequential carrier (BSC) is a 16-bit general register that you can manipulate using 1-, 4-, and 8-bit RAM
control instructions.
Using the BSC register, addresses and bit locations can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.
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S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
C
IS0
SC2
EMB
SC1
ERB
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, … or 15) and store the upper four bits of the 12-bit data
..,
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a Crystal, Ceramic, or RC oscillation source, or an externally-
generated clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce four CPU clock frequencies —
fx/4, fx/8, fx/64, or fxt/4.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, INT4, and INTK). There are two quasi-interrupts: INT2 and INTW.
INT2 detects rising or falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91
milliseconds. The following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
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