This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated
with the high performance CMOS process,and is ideal for large-
capacity memory systems where high speed, low power dissipation,
and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery back-up
application.
PIN CONFIGURATION (TOP VIEW)
DQ
1
1
DQ
2
2
W 3
RAS 4
A
9
5
26 V
SS
25 DQ
4
24 DQ
3
23 CAS
22 OE
FEATURES
A
0
9
18 A
8
17 A
7
16 A
6
15 A
5
14 A
4
Type name
M5M44405CXX-5,-5S
M5M44405CXX-6,-6S
M5M44405CXX-7,-7S
RAS
CAS
access
access
time
time
(max.ns) (max.ns)
Address
OE
Cycle
Power
access
access
time
dissipa-
time
time
tion
(max.ns) (max.ns) (min.ns) (typ.mW)
A
1
10
A
2
11
A
3
12
V
CC
13
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
500
400
350
XX=J,TP
Outline 26P0J (300mil SOJ)
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 5V±10%supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max) *
CMOS lnput level
550µW (Max)
Low operating power dissipation
M5M44405Cxx-5,-5S
687.5mW (Max)
M5M44405Cxx-6,-6S
550.0mW (Max)
M5M44405Cxx-7,-7S
467.5mW (Max)
Self refresh capabiility *
Self refresh current
120µA(max)
Extended refresh capability *
Extended refresh current
120µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-5S,-6S,-7S) capabilities
Early-write mode and OE and W to control output buffer impedance
All inputs, output TTL compatible and low capacitance
1024 refresh cycles every 16.4ms (A
0
~A
9
)
1024refresh cycle every 128ms (A
0
~A
9
) *
4-bit parallel test mode capability
* : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S
: option) only
DQ
1
1
DQ
2
2
W 3
RAS 4
A
9
5
26 V
SS
25 DQ
4
24 DQ
3
23 CAS
22 OE
A
0
9
A
1
10
A
2
11
A
3
12
V
CC
13
18 A
8
17 A
7
16 A
6
15 A
5
14 A
4
Outline 26P3Z-E (300mil TSOP)
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name
A
0
~A
9
DQ
1
~DQ
4
RAS
CAS
W
OE
Vcc
Vss
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+5V)
Ground (0V)
1
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
FUNCTION
The M5M44405CJ, TP provide, in addition to normal read, write,
and read-modify-write operations,a number of other functions, e.g.,
hyper page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Self refresh *
Stand-by
Inputs
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
W
NAC
ACT
ACT
ACT
DNC
DNC
NAC
NAC
DNC
OE
ACT
DNC
NAC
ACT
DNC
ACT
DNC
DNC
DNC
Row
address
Column
address
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
Input/Output
Output
Input
OPN
VLD
APD
OPN
APD
IVD
APD
VLD
DNC
OPN
OPN
VLD
DNC
OPN
DNC
OPN
DNC
OPN
Refresh Remark
YES
YES
YES
YES
YES
YES
YES
YES
NO
Hyper-
Page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT CAS
ROW ADDRESS RAS
STROBE INPUT
WRITE CONTROL
INPUT
W
A
0
~A
9
V
CC
(5V)
CLOCK GENERATOR
CIRCUIT
V
SS
(0V)
COLUMN DECODER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
(4)
DATA IN
BUFFERS
DQ
1
SENSE REFRESH
AMPLIFER & I /O CONTROL
DQ
2
DQ
3
DQ
4
(4)
DATA OUT
BUFFERS
DATA
INPUTS / OUTPUTS
ADDRESS INPUTS
ROW &
COLUMN
ADDRESS
BUFFER
ROW
A
0
~
A
9
DECODER
MEMORY CELL
(4,194,304 BITS)
OE OUTPUT ENABLE
INPUT
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ratings
-
1~7
-
1~7
-
1~7
50
1000
0~70
-
65~150
Unit
V
V
V
mA
mW
˚C
˚C
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0~70˚C, unless otherwise noted)
(Note 1)
Symbol
V
CC
V
SS
V
IH
V
IL
Supply voltage
Supply voltage
High-level input voltage, all inputs
DQ
1
~
4
Low-level input voltage
others
Parameter
Limits
Min
4.5
0
2.4
-
1.0
-
2.0
Nom
5
0
Max
5.5
0
6.0
0.8
0.8
Unit
V
V
V
V
V
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS
(Ta=0~70˚C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted)
Symbol
V
OH
V
OL
I
OZ
I
I
I
CC1 (AV)
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current
I
OH
=–5mA
I
OL
= 4.2mA
Q floating 0V
≤
V
OUT
≤
5.5V
0V
≤
V
IN
≤
+6.5V,
Other inputs pins=
0V
Test conditions
(Note 2)
Min
2.4
0
-10
-10
Limits
Typ
I
CC2 (AV)
I
CC3 (AV)
M5M44405C-5,-5S
RAS, CAS cycling
Average supply current
from Vcc, operating
M5M44405C-6,-6S
t
RC
=t
WC
=min.
(Note 3,4,5)
M5M44405C-7,-7S
output open
RAS= CAS =V
IH
, output open
Supply current from Vcc ,
RAS= CAS
≥
V
CC
–0.5V
stand-by
(Note 6)
M5M44405C
output open
M5M44405C(S)
Average supply current
M5M44405C-5,-5S
RAS cycling, CAS= V
IH
from Vcc, refreshing
M5M44405C-6,-6S
t
RC
=min.
(Note 3,5)
M5M44405C-7,-7S
output open
M5M44405C-5,-5S
Average supply current
from Vcc, Hyper-Page-
M5M44405C-6,-6S
Mode
(Note 3,4,5)
M5M44405C-7,-7S
M5M44405C-5,-5S
Average supply current
from Vcc, CAS before
M5M44405C-6,-6S
RAS refresh mode (Mote 3)
M5M44405C-7,-7S
RAS=V
IL
, CAS cycling
t
PC
=min.
output open
CAS before RAS refresh cycling
t
RC
=min.
output open
RAS
cycling
CAS
≤
0.2V or CAS
before RAS refresh cycling
RAS
≤
0.2V or
≥
V
CC
-0.2V
CAS
≤
0.2V or
≥
V
CC
-0.2V
W
≤
0.2V(Except for RAS falling edge)
or V
CC
-0.2V
OE
≤
0.2V or
≥
V
CC
-0.2V
A
0
~A
9
≤
0.2V or
≥
V
CC
-0.2V,
DQ=open
t
RC
=125µs,
t
RAS
=
t
RAS min
~1µs
I
CC4(AV)
Max
Vcc
0.4
10
10
125
100
85
2
1
0.1
125
100
85
125
100
85
105
85
75
Unit
V
V
µA
µA
mA
mA
mA
mA
I
CC6(AV)
mA
I
CC8(AV)
Average supply current
from Vcc,
Extended-Refresh cycle
(Note 6)
120
µA
I
CC9(AV)
Average supply current
from Vcc, Self-Refresh
cycle
(Note 6)
M5M44405C(S)
RAS=CAS
≤
0.2V
output open
120
µA
Note 2 : Current flowing into an IC is positive, out is negative.
Note
3 : I
CC1(AV)
, I
CC3 (AV)
, I
CC4(AV)
and I
CC6(AV)
are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
Note
4 : I
CC1(AV)
and I
CC4(AV)
are dependent on output loading. Specified values are obtained with the output open.
Note
5 : Column Address can be changed once or less while RAS=V
IL
and CAS=V
IH
.
3
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
CAPACITANCE
(Ta=0~70˚C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted)
Symbol
C
I (A)
C
I (CLK)
C
I / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
V
I
=V
SS
f=1MHz
V
I
=25mVrms
Min
Limits
Typ
Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS
(Ta=0~70˚C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,14,15)
Limits
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
OHC
t
OHR
t
CLZ
t
OEZ
t
WEZ
t
OFF
t
REZ
Parameter
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
5
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
5
5
13
13
13
13
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
13
50
25
28
13
Min
Max
15
60
30
33
15
Min
Max
20
70
35
38
20
5
5
5
15
15
15
15
5
5
5
20
20
20
20
Note 6 : An initial pause of 200µs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause . And eight initialization cycles are required after prolonged periods (greater than
t
REF(max)
) of RAS
inactivity before proper device operation is achieved.
Note
7 : Measured with a load circuit equivalent to 2TTL and 100pF.
The reference levels for measuring of output signals are 2.0V(V
OH
) and 0.8V(V
OL
).
Note
8 : Assumes that
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
and
t
CP
≥
t
CP(max)
.
Note
9 : Assumes that
t
RCD
≤
t
RCD(max)
and
t
RAD
≤
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will
increase by amount that
t
RCD
exceeds the value shown.
Not
10 : Assumes that
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
.
No t11
: Assumes that
t
CP
≤
t
CP(max)
and
t
ASC
≥
t
ASC(max)
.
No t12
:
t
OEZ(max)
,
t
WEZ(max)
,
t
OFF(max)
and
t
REZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
±10µA ) and is not
reference to V
OH(min)
or V
OL(max)
.
Not
13 : Output is disabled after both RAS and CAS go to high.
4
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
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MCU
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