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3PV750BW-FREQ

Description
PECL Output Clock Oscillator, 40MHz Min, 170MHz Max
CategoryPassive components    oscillator   
File Size43KB,1 Pages
ManufacturerPletronics
Download Datasheet Parametric Compare View All

3PV750BW-FREQ Overview

PECL Output Clock Oscillator, 40MHz Min, 170MHz Max

3PV750BW-FREQ Parametric

Parameter NameAttribute value
Reach Compliance Codeunknown
Other featuresDIFFERENTIAL PECL OUTPUT WITH ENABLE/DISABLE FUNCTION
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time1 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate100 ppm
frequency stability50%
Manufacturer's serial numberPV7
Installation featuresSURFACE MOUNT
Maximum operating frequency170 MHz
Minimum operating frequency40 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typePECL
Output load50 OHM
physical size7mm x 5mm x 2mm
longest rise time1 ns
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry60/40 %
Base Number Matches1
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
PV7 PECL VCXO Series
6 Pad Leadless Ceramic Surface Mount PECL Voltage Controlled Xtal Oscillator
40.00 MHz
170.00 MHz
Differential PECL Output with Enable/Disable
Consult factory for
higher
frequencies
Standard Specifications
Overall Frequency Stability
Operating Temperature Range
Supply Voltage (Vcc)
Supply Current (Icc)
Jitter
Output Load
Enable/Disable Option (E/D)
Control Voltage Range (CVR)
Pullablity over CVR
Linearity
Output Waveform
PECL with Differential Output
± 50 PPM over Operating Temperature Range
0 to +70°C
3.3 volts ± 10% standard, consult factory for 5.0 volts
100 mA maximum
1 pS RMS maximum,
from 12 kHz to 20 MHz from carrier
Output must be terminated into 50 ohms to (Vdd - 2.0 V). See Test Circuit 10 and Note 1.
Output enabled when Pin #2 is open or at CMOS Logic “1”;
Output disabled when Pin #2 is at CMOS Logic “0”.
0.0 to 3.3 volts
± 100 PPM or
± 50 PPM
Consult factory
Symmetry
40/60% to 60/40% at 50% of Vcc level (see Waveform 2)
Tr & Tf
1.0 nS max
Logic “1”
Vcc - 1.02 volts minimum
Logic “0”
Vcc - 1.63 volts maximum
Note 1: In the typical PECL 100K logic output Voh is 2.35 volts and Vol is 1.60 volts at 3.3 Vcc. The center voltage of the PECL is therefore 1.975 volts.
If a 50
W
resistor is placed between the output and Vdd – 2 volts (1.3 volts), the current through the resistor is (1.975 – 1.3) / 50 = 13.5 mA.
The same load can be simulated by a resistor of 147 ± 1% ohms to ground (1.975 / 0.0135 = 146.29 ohms). If additional load current is placed
on the output, its load current must be subtracted from the 13.5 mA to calculate a new load resistor. Using similar calculations, use 274 ± 1%
ohms to ground for 5.0V operation.
Part Numbering Guide
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)
Packaging
Tray or
16mm tape
8mm pitch
3 PV7 50 B W - 155.52M - XXX
(Internal Code or blank)
Supply Voltage
Blank= 5.0 volts ±10%
3= 3.3 volts ±10%
Model
Frequency Stability
50 = ± 50 PPM
Frequency in MHz
Frequency Deviation (Pullability) over CVR
V: ± 50 PPM
W: ± 100 PPM
Operating Temperature Range
B: 0 to +70
°
C
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load
not to scale
Mechanical:
size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.
Due to part
inches (mm)
Solder Pads
.08 .09 .08
(2.0)(2.2)(2.0)
.276 (7.0 ± .2)
3
4
OUT
5
C OUT
6
Vdd
.200 (5.08)
Vss
For Best Performance,
Do NOT allow any traces other
than ground under oscillators
(Even in buried layers). See
Page 4A for layout guidelines.
4
5
6
3
2
1
.063 (1.6)
0.01
m
F
bypass capacitor
Feb 2004
E/D
2
PLE
Vcon
1
.197
(5.0 ± .2)
.079 (2.0)
MAX
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
TBD
PECL, ECL, LVDS
Page 1 - 7
Pl tronics, Inc.
.

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Description PECL Output Clock Oscillator, 40MHz Min, 170MHz Max PECL Output Clock Oscillator, 40MHz Min, 170MHz Max PECL Output Clock Oscillator, 40MHz Min, 170MHz Max
Reach Compliance Code unknown unknown compliant
Other features DIFFERENTIAL PECL OUTPUT WITH ENABLE/DISABLE FUNCTION DIFFERENTIAL PECL OUTPUT WITH ENABLE/DISABLE FUNCTION DIFFERENTIAL PECL OUTPUT WITH ENABLE/DISABLE FUNCTION
Maximum control voltage 3.3 V 3.3 V 3.3 V
maximum descent time 1 ns 1 ns 1 ns
Frequency Adjustment - Mechanical NO NO NO
Frequency offset/pull rate 100 ppm 50 ppm 100 ppm
frequency stability 50% 50% 50%
Manufacturer's serial number PV7 PV7 PV7
Installation features SURFACE MOUNT SURFACE MOUNT SURFACE MOUNT
Maximum operating frequency 170 MHz 170 MHz 170 MHz
Minimum operating frequency 40 MHz 40 MHz 40 MHz
Maximum operating temperature 70 °C 70 °C 70 °C
Oscillator type PECL PECL PECL
Output load 50 OHM 50 OHM 50 OHM
physical size 7mm x 5mm x 2mm 7mm x 5mm x 2mm 7mm x 5mm x 2mm
longest rise time 1 ns 1 ns 1 ns
Nominal supply voltage 3.3 V 3.3 V 5 V
surface mount YES YES YES
maximum symmetry 60/40 % 60/40 % 60/40 %
Base Number Matches 1 1 -
Maker - Pletronics Pletronics

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