M54HCT08 datasheet, PDF - EEWORLD Datasheet

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M54HCT08: DescriptionQUAD 2-INPUT AND GATE; File Size220KB，9 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M54HCT08 Overview

QUAD 2-INPUT AND GATE

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M54HCT08

M74HCT08

QUAD 2-INPUT AND GATE

HIGH SPEED

= 12 ns (TYP.) AT V

= 5 V

LOW POWER DISSIPATION

= 1

µA

(MAX.) AT T

= 25

°C

COMPATIBLE WITH TTL OUTPUTS

= 2V (MIN.) V

= 0.8V (MAX)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I



= I

= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

PLH

= t

PHL

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS08

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

DESCRIPTION

The M54/74HCT08 is a high speed CMOS QUAD

2-INPUT AND GATE fabricated in silicon gate

MOS technology. It has the same high speed per-

formance of LSTTL combined with true CMOS low

power consumption. The internal circuit is com-

posed of 2 stages including buffer output, which

gives high noise immunity and stable output. All in-

puts are equipped with protection circuits against

static discharge and transient excess voltage.

This integrated circuit has input and output charac-

teristics that are fully compatible with 54/74 LSTTL

logic families. M54/74HC devices are designed to

directly interface HSC

MOS systems with TTL and

NMOS components. They are also plug in replace-

ments for LSTTL devices giving a reduction of

power consumption.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

ORDER CODES :

M54HCT08F1R

M74HCT08M1R

M74HCT08B1R

M74HCT08C1R

PIN CONNECTIONS

(top view)

NC =

No Internal

Connection

February 1993

1/9

M54HCT08 Related Products

	M54HCT08	M74HCT08C1R	M54HCT08F1R
Description	QUAD 2-INPUT AND GATE	QUAD 2-INPUT AND GATE	QUAD 2-INPUT AND GATE
Is it Rohs certified?	-	conform to	incompatible
Maker	-	STMicroelectronics	STMicroelectronics
Parts packaging code	-	QFN	DIP
package instruction	-	PLASTIC, CC-20	DIP, DIP14,.3
Contacts	-	20	14
Reach Compliance Code	-	compli	_compli
series	-	HCT	HCT
JESD-30 code	-	S-PQCC-J20	R-GDIP-T14
JESD-609 code	-	e3	e0
Load capacitance (CL)	-	50 pF	50 pF
Logic integrated circuit type	-	AND GATE	AND GATE
MaximumI(ol)	-	0.004 A	0.004 A
Number of functions	-	4	4
Number of entries	-	2	2
Number of terminals	-	20	14
Maximum operating temperature	-	85 °C	125 °C
Minimum operating temperature	-	-40 °C	-55 °C
Package body material	-	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	-	QCCJ	DIP
Encapsulate equivalent code	-	LDCC20,.4SQ	DIP14,.3
Package shape	-	SQUARE	RECTANGULAR
Package form	-	CHIP CARRIER	IN-LINE
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED
power supply	-	5 V	5 V
Prop。Delay @ Nom-Su	-	26 ns	32 ns
propagation delay (tpd)	-	26 ns	32 ns
Certification status	-	Not Qualified	Not Qualified
Schmitt trigger	-	NO	NO
Maximum seat height	-	4.57 mm	5.08 mm
Maximum supply voltage (Vsup)	-	5.5 V	5.5 V
Minimum supply voltage (Vsup)	-	4.5 V	4.5 V
Nominal supply voltage (Vsup)	-	5 V	5 V
surface mount	-	YES	NO
technology	-	CMOS	CMOS
Temperature level	-	INDUSTRIAL	MILITARY
Terminal surface	-	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	-	J BEND	THROUGH-HOLE
Terminal pitch	-	1.27 mm	2.54 mm
Terminal location	-	QUAD	DUAL
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED
width	-	8.9662 mm	7.62 mm

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