M54HC597
M74HC597
8 BIT LATCH/SHIFT REGISTER
.
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 60 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
µA
(MAX.) AT T
A
= 25
°C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS597
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC597F1R
M74HC597M1R
M74HC597B1R
M74HC597C1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC597 is a high speed CMOS 8-BIT
LATCH/SHIFT REGISTER fabricated in silicon gate
2
C MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
This devices comes in a 16-pin package and consist
of an 8-bit storage latch feeding a parallel-in, serial-
out 8-bit shift register. Both the storage register and
shift register have positive-edge triggered clocks.
The shift register also has direct load (from storage)
and clear inputs.
All inputs are equipped with protection circuits
against static discharge and transient voltage ex-
cess.
October 1992
NC =
No Internal
Connection
1/13
M54/M74HC597
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
SI
X
X
L
H
X
X
X
X: DON’T CARE
SCK
X
X
SCLR
L
H
H
H
H
SLOAD
H
L
H
H
H
X
X
RCK
X
X
X
X
X
OUTPUT
S.R. IS CLEARED TO ”L”
INPTU REGISTER DATA IS STORED INTO S.R.
FIRST STAGE OF S.R. BECOMES ”L” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES ”H” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
STATE OF S.R IS NOT CHANGED
INPUT DATA ON A ~ H LINE IS STORED INTO INPUT
REGISTER
STORAGE REGISTER STATE IS NOT CHANGED
X
X
X
X
LOGIC DIAGRAM
2/13
M54/M74HC597
PIN DESCRIPTION
PIN No
9
10
11
12
SYMBOL
QH’
SCLR
SCK
RCK
NAME AND FUNCTION
Serial Data Outputs
Asynchronous Reset
Input (Active LOW)
Shift Clock Input (LOW
to HIGH Edge-triggered)
Storage Clock Input
(LOW to HIGH
Edge-triggered)
Parallel Data Input
(Active LOW)
Serial Data Input
Parallel Data Inputs
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOL
13
10
15, 1, 2, 3,
4, 5, 6, 7
8
16
SLOAD
SI
A to H
GND
V
CC
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
D
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
DC V
CC
or Ground Current
Power Dissipation
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
500 (*)
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
mW
o
o
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW:
≅
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
t
r
, t
f
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature:
M54HC
Series
M74HC
Series
Input Rise and Fall Time
Value
2 to 6
0 to V
CC
0 to V
CC
-55 to +125
-40 to +85
0 to 1000
0 to 500
0 to 400
Unit
V
V
V
C
o
C
ns
o
V
CC
= 2 V
V
CC
= 4.5 V
V
CC
= 6 V
5/13
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