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AN10145: DescriptionBi-directional low voltage translators; File Size314KB，24 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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Bi-directional low voltage translators

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INTEGRATED CIRCUITS

REF

ABSTRACT

Philips Semiconductors Gunning Transceiver Logic Translator Voltage Clamp (GTL-TVC)

bi-directional low voltage translators are used in bi-directional signaling voltage level translation

applications. Voltage translation can be from any voltage between 1.0 V to 5.0 V to any voltage

between 1.0 V to 5.0 V without need for directional control. Device operation, resistor sizing and

typical applications are discussed in this application note.

AN10145

Bi-directional low voltage translators

GTL2000, GTL2002, GTL2010

Supersedes data of 2002 Dec 16

Alma Anderson – Senior Design Engineer

Jean-Marc Irazabal – Technical Marketing Manager

Steve Blozis – International Product Manager

Specialty Logic Product Line

Interface Products Business Line

2004 Aug 11

Philips

Semiconductors

TABLE OF CONTENTS

TABLE OF CONTENTS ...................................................................................................................................................2

OVERVIEW .......................................................................................................................................................................3

ESCRIPTION

.....................................................................................................................................................................3

PPLICATIONS

...................................................................................................................................................................3

EATURES

.........................................................................................................................................................................5

PERATING

HARACTERISTICS

.........................................................................................................................................6

EVICE

INOUT

.................................................................................................................................................................6

RDERING

NFORMATION

..................................................................................................................................................7

ATA

HEETS AND

IBIS M

ODELS

.....................................................................................................................................7

TECHNICAL INFORMATION .......................................................................................................................................7

LOCK

IAGRAM

..............................................................................................................................................................7

ALCULATING

ULL

-U

ESISTOR

ALUES

...................................................................................................................13

APPLICATIONS..............................................................................................................................................................14

OLTAGE

EVEL

RANSLATION

.....................................................................................................................................14

FREQUENTLY ASKED QUESTIONS .........................................................................................................................15

EVICE

............................................................................................................................................................................15

ONNECTING THE DEVICE TO THE RIGHT VOLTAGES

COMPONENTS

.................................................................................16

PPLICATIONS

.................................................................................................................................................................17

ADDITIONAL INFORMATION ...................................................................................................................................23

OVERVIEW

Description

Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the

input voltage (V

or V

) and output voltage (V

or V

) typically based on the device operating voltage. These voltage

levels define how the device communicates with other devices and the voltage levels are expressed as a bus standard. A

few of these bus standards include 5 V CMOS, 5 V TTL, 3.3 V LVTTL, 2.5 V AGP graphics port and 1.5 V GTL+ host

bus. Providing a migration path is important in all industry segments because system components used in new designs

must communicate with components using the existing bus infrastructure even if they are operating at higher voltage

levels. Since new devices are designed and produced with advanced sub-micron semiconductor process technologies,

there has to be an easy way to prevent damage to the new device and translate voltage switching levels of the higher

voltage legacy device.

The Philips Semiconductors Gunning Transceiver Logic Translator Voltage Clamp (GTL-TVC) family of bi-directional

low voltage translators is designed in a BiCMOS process for protecting the sensitive I/Os on new advanced sub micron

components. The GTL-TVC devices protect these new devices from the over voltage and ESD conditions applied by the

older, legacy devices and translate the V

and V

switching levels. The information presented in this application note

describes the I/O-protection applications and voltage translations of the GTL-TVC family and will enable the design

engineer to successfully interface devices with different I/O voltage levels.

Applications

Voltage Level Shifting

The GTL-TVC devices can be used to interface between devices I/Os operating at different voltage levels. Since the

GTL-TVC device is open drain on both sides, pull up resistors may be needed depending on the I/O interface type (totem

pole or open drain) and the translation direction (High to Low, Low to High, or bi-directional). The GTL-TVC devices

allow translations between any voltages from 1.0 V to 5.0 V as long as the voltage difference between the Gate and

Source voltages is maintained at about 1 V. The recommended circuit in Figure 1 connects the gate (GREF) and

reference drain (DREF) together through a 200 k

Ω

resistor to a voltage,

which should be at least 1.5 V above the

reference Source (SREF) level.

This circuit biases the gate to a threshold above the reference source voltage and

compensates for part-to-part threshold variations. Since the gate threshold voltage can vary between 0.6 V and 1 V, if the

GREF to SREF voltage is less than 1 V, the low voltage side high level may be degraded below the SREF voltage

because it can only pull up to a threshold below the GREF voltage.

1.8 V

1.5 V

1.2 V

1.0 V

200 kΩ

GTL200

GND GREF

SREF DREF

COR

CPU

I/O

Chipset I/O

Figure 1. Typical Two-bit bi-directional application

Bi-directional Translation

For bi-directional translation, the drivers on both sides of the GTL-TVC device must be open drain outputs or at

least they must be controlled in such a way that contention between a High level on an output driver on one side

and a Low level on an output driver on the other side is prevented. The easiest solution is to use open drain

devices (the standard GTL and I

C/SMBus outputs are open drain outputs).

When using open drain devices, it is necessary to use pull up resistors, and they must be sized so as not to

overload the output drivers nor exceed the 15 mA recommended current for use of a GTL-TVC device in a

translation application. If the device is used for I

C bus translation, the resistors must be sized to provide less

than 3 mA of current (I

C devices are specified to drive 3 mA max at 0.4 V).

When the GTL-TVC device is used as described in Figure 1, it is not necessary to have pull up resistors on the

lower voltage side because the GTL-TVC device will pass up to the reference Source voltage. With a 200 kΩ

resistor connected to the reference Drain (DREF) and the reference Gate (GREF) and pulled up to a supply

voltage

that is at least 1.5 V higher than the reference Source (SREF) level,

about 2.5

µA

will pass to the

lower voltage side at the reference Source voltage value. If the low voltage side is known to be leaky (more than

the 2.5

µA

described above), it is necessary to include a pull up resistor on the low voltage side as well as the

high voltage side to provide the required current value.

Down Translation

When doing down translation, since there is no driver on the lower voltage side, the higher voltage driver may

be either totem pole without any pull up resistor or open drain with a pull up resistor, and

no resistor pull up is

needed on the low voltage side

unless it has excessive leakage (more than the 2.5

µA

described in the

paragraph above).

Up Translation

A pull up resistor is

always

required on the higher voltage side to get the full high level, since the GTL-TVC

device will only pass the reference source voltage as a high when doing a up translation. A full CMOS driver or

an open drain driver with or without a pull up resistor on the low voltage side may be used. The resistor values

must be chosen so as not to overload the pull down driver nor the 15 mA limit of the GTL-TVC devices.

Multiple Voltage Bi-Directional Translation

The channel pass transistors are constructed such that the gate of the reference transistor (GREF) pin is used to

limit the maximum high voltage that will be passed by the device. This allows the use of different bus voltages

on each source to drain channel so that for example, a 1.5 V device can communicate with 2.5 V, 3.3 V or 5 V

devices without any additional protection. Figure 2 shows how the GTL2010 can be used in a bi-directional I

application where two ASIC’s I

C ports (left side) operating at 1.5 V can interface to higher voltage devices

(right side) operating at 3.3V and 5.0 V.

- One of the ASIC ports (MDDC on S1 & S2) only needs to interface with 5 V I

C devices.

- The other ASIC port (MI2C on S3 & S4 and S5 & S6) needs to interface with both 3.3 V SMBus and 5.0 V

C devices.

Since the voltage difference between the low voltage (1.5V, left side) and the voltage on the resistor for the

GREF (Gate pull-up) is higher than 1.5V (5.0V in the figure), pull up resistors on the low voltage side (1.5V)

are optional.

Note:

Pull up resistors on the low voltage side are required if:

Te difference between the external voltage applied on the resistor for the Gate reference (GREF) and

the voltage on the low side is lower than 1.5V

The device in the low voltage side has a leakage current value higher than 2.5

µA

Figure 2. Bi-directional Multiple Voltage I

C Application

Cross-Bar Technology (CBT) Like Behavior

The large NMOS pass transistors used in the GTL-TVC devices are very similar to the large NMOS pass transistors used

in CBT devices. However unlike the CBT devices that use internal drivers to control the gate of the NMOS pass

transistor, the gate pin of the GTL-TVC devices is directly connected to the gate of each transistor. In principle the

GTL-TVC devices can be used like CBT devices except that the gate input capacitance is much larger than a normal

CBT device. When using the GTL-TVC devices as CBT devices, the gate pin (GREF) is driven by external logic to the

power supply, to enable it, or to ground to disable it, and the SREF and DREF pins can be used as an additional channel

as shown in Figure 3.

GTL2002

GND GREF

SREF DREF

Control

Chip set

Chipset I/O

Figure 3. Cross Bar Technology like Application

Note:

If a 5 V to 3.3 V translation is wanted, best results are achieved using the bias circuit of the GTL-TVC with the

SREF at 3.3 V. Additionally, when used as a CBT function with the gate at V

and the input at V

DD,

the maximum pass

voltage will be ~ V

– 1 V because the output is shifted down by a threshold compared to the gate voltage.

Features

The GTL-TVC family has several features that benefit a system designer when designing an interface between devices

with different I/O voltage levels.

Device Construction

– The GTL-TVC devices are of a very simple design. The only required connections are GND,

gate of the reference transistor (GREF), drain of the reference transistor (DREF) and source of the reference transistor

(SREF) and then any of the Dn/Sn I/O pairs needed for voltage level translations.

•

Any transistor Dn or Sn I/O pair can be used as the source or drain of the reference transistor (SREF or DREF). This

makes it easier to route signals to and from the device.

•

All the transistors are on one die, which is manufactured with very tight process control. This provides a very low

spread of V

relative to SREF or DREF.

•

It is easy to change the SREF voltage allowing the system designer an easy migration path to even lower voltages

(e.g. 1.5 V or 1.2 V).

•

Dn /Sn I/O pairs are matched on either side of the devices (e.g., flow through pinout) which offers easy trace

routing.

No Active Control Logic

– As shown in Figure 4, the GTL-TVC is a passive device and there is no active control logic.

This means there is no supply power (V

) required for device operation.

Figure 4. GTL20XX Logic Diagram

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