The VS-702 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes on
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as
shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Figure 3 Standard PECL Output Con guration
Figure 4 Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms
Figure 5 Pull-Up Pull-Down Termination
Reliability
VI quali cation includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR re ow
simulation. The VS-702 family is capable of meeting the following quali cation tests:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Mechanical Vibration
Conditions
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2015
MSL 1
Gold over Nickel
MIL-STD-883,
Typical Characteristics - Phase Noise
Method 2002
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not
implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.
Exposure to absolute maximum ratings for extended periods may adversely a ect device reliability. Permanent damage is
also possible if OD or Vc is applied before Vcc.
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Output Current
Voltage Control Range
Storage Temperature
Soldering Temp/Time
Symbol
V
DD
I
OUT
V
C
TS
T
LS
Ratings
0 to 6
25
0 to V
DD
-55 to 125
260 / 40
Unit
V
mA
V
°C
°C / sec
Although ESD protection circuitry has been designed into the VS-702 proper precautions should be taken when handling
and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing
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