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ADC128S102QML 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter
October 27, 2009
ADC128S102QML
8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter
General Description
The ADC128S102 is a low-power, eight-channel CMOS 12-
bit analog-to-digital converter specified for conversion
throughput rates of 50 kSPS to 1 MSPS. The converter is
based on a successive-approximation register architecture
with an internal track-and-hold circuit. It can be configured to
accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with
several standards, such as SPI™, QSPI™, MICROWIRE™,
and many common DSP serial interfaces.
The ADC128S102 may be operated with independent analog
and digital supplies. The analog supply (V
A
) can range from
+2.7V to +5.25V, and the digital supply (V
D
) can range from
+2.7V to V
A
. Normal power consumption using a +3V or +5V
supply is 2.3 mW and 10.7 mW, respectively. The power-
down feature reduces the power consumption to 0.06 µW
using a +3V supply and 0.25 µW using a +5V supply.
Features
■
■
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■
■
■
■
Total Ionizing Dose
100 krad(Si)
Single Event Latch-up
120 MeV-cm
2
/mg
Eight input channels
Variable power management
Independent analog and digital supplies
SPI/QSPI/MICROWIRE/DSP compatible
Packaged in 16-lead Ceramic SOIC
Key Specifications
■
■
■
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Conversion Rate
DNL (V
A
= V
D
= 5.0 V)
INL (V
A
= V
D
= 5.0 V)
Power Consumption
—
3V Supply
—
5V Supply
50 kSPS to 1 MSPS
+1.5 / −0.9 LSB (max)
+1.4 / −1.25 LSB (max)
2.3 mW (typ)
10.7 mW (typ)
Applications
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Automotive Navigation
Portable Systems
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Ordering Information
NS PART NUMBER
ADC128S102WGRQV
SMD PART NUMBER
5962R0722701VZA
100 krad(Si)
NS PACKAGE NUMBER
WG16A
PACKAGE DISCRIPTION
16LD Ceramic SOIC
Connection Diagram
30018105
SPI™ is a trademark of Motorola, Inc.
© 2009 National Semiconductor Corporation
300181
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ADC128S102QML
Block Diagram
30018107
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
4 - 11
DIGITAL I/O
16
SCLK
Digital clock input. The guaranteed performance range of
frequencies for this input is 0.8 MHz to 16 MHz. This clock directly
controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin
on the falling edges of the SCLK pin.
Digital data input. The ADC128S102QML's Control Register is
loaded through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process
begins. Conversions continue as long as CS is held low.
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet +2.7V
to +5.25V source and bypassed to GND with 1 µF and 0.1 µF
monolithic ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a +2.7V
to V
A
supply, and bypassed to GND with a 0.1 µF monolithic
ceramic capacitor located within 1 cm of the power pin.
The ground return for the analog supply and signals.
The ground return for the digital supply and signals.
IN0 to IN7
Analog inputs. These signals can range from 0V to V
REF
.
Symbol
Equivalent Circuit
Description
15
14
1
POWER SUPPLY
DOUT
DIN
CS
2
V
A
13
3
12
V
D
AGND
DGND
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2
ADC128S102QML
Absolute Maximum Ratings
(Note
1)
Analog Supply Voltage V
A
Digital Supply Voltage V
D
Voltage on Any Pin to GND
Input Current at Any Pin (Note
3)
Power Dissipation (Note
4)
Package Input Current (Note
3)
ESD Susceptibility (Note
5)
Human Body Model
Soldering Temperature
10 seconds
Junction Temperature
Storage Temperature
−0.3V to 6.5V
−0.3V to V
A
+ 0.3V,
max 6.5V
−0.3V to V
A
+0.3V
±10 mA
T
A
= 25°C
±20 mA
(Class 3A) 8000V
260°C
+175°C
−65°C to +150°C
Operating Ratings
Operating Temperature
T
MIN
T
MAX
V
A
Supply Voltage
V
D
Supply Voltage
Digital Input Voltage
Analog Input Voltage
Clock Frequency
(Note
1, Note 2)
−55°C
+125°C
+2.7V to +5.25V
+2.7V to V
A
0V to V
A
0V to V
A
0.8 MHz to 16 MHz
Package Thermal Resistance
Package
16-lead Cerpack
Gullwing
θ
JA
127°C/W
θ
JC
11.2°C/ W
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
1
2
3
4
5
6
7
8A
8B
9
10
11
12
13
14
Description
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
Setting time at
Setting time at
Temp (°C)
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
3
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ADC128S102QML
ADC128S102QML Converter Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 16 MHz, f
SAMPLE
= 50 kSPS to 1 MSPS, C
L
= 50pF,
unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol
Parameter
Conditions
Notes
Typical
(Note
6)
Min
Max
Units
Sub-
groups
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing
Codes
INL
Integral Non-Linearity (End
Point Method)
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V
DNL
Differential Non-Linearity
V
A
= V
D
= +5.0V
V
OFF
OEM
FSE
FSEM
Offset Error
Offset Error Match
Full Scale Error
Full Scale Error Match
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V
V
A
= V
D
= +5.0V
V
A
= V
D
= +3.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +5.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +3.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +5.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +3.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +5.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +3.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +5.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +3.0V,
f
IN
= 40.2 kHz
V
A
= V
D
= +5.0V,
f
IN
= 40.2 kHz, −0.02 dBFS
V
A
= V
D
= +3.0V,
f
IN
= 20 kHz
V
A
= V
D
= +5.0V,
f
IN
= 20 kHz, −0.02 dBFS
±0.6
±0.9
+0.5
−0.3
+0.9
−0.5
+0.8
+1.1
±0.1
±0.3
+0.8
+0.3
±0.1
±0.3
6.8
10
72
72
72
72
−86
−87
91
90
11.6
11.6
84
85
75
75
11.1
11.1
68
68
69
68.5
−74
−74
−0.9
−2.3
−2.3
−1.5
−1.5
−2.0
−2.0
−1.5
−1.5
+2.3
+2.3
+1.5
+1.5
+2.0
+2.0
+1.5
+1.5
−0.7
+1.5
−1.0
−1.25
12
+1.1
+1.4
+0.9
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MHz
MHz
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
dB
dB
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
(−3dB)
Signal-to-Noise Plus
Distortion Ratio
SINAD
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
SFDR
Spurious-Free Dynamic
Range
ENOB
Effective Number of Bits
ISO
Channel-to-Channel
Isolation
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Embedded System
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