INTEGRATED CIRCUITS
74ALVCH16823
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
Product specification
IC24 Data Handbook
1998 Jul 29
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
Multibyte™flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins to minimize noise and
ground bounce
DESCRIPTION
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-state outputs for bus
oriented applications. Incorporates bushold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs. The74ALVCH16823 consists of two sections of nine
edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)
input, a Master reset (MR) input and a clock-enable( CE) input are
provided for each total 9-bit section.
With the clock-enable (CE) input LOW, the D-type flip-flops will store
the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition. Taking CE
HIGH disables the clock buffer, thus latching the outputs. Taking the
Master reset (MR) input LOW causes all the Q outputs to go LOW
independently of the clock.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When the OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
•
All data inputs have bus hold
•
Output drive capability 50Ω transmission lines @ 85°C
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
SYMBOL
t
PHL
/t
PLH
F
max
C
I
C
PD
PARAMETER
Propagation delay
CP to Qn
Maximum clock frequency
Input capacitance
Power dissipation capacitance per latch
V
I
= GND to V
CC1
Outputs enabled
Outputs disabled
CONDITIONS
V
CC
= 2.5V, CL = 30pF
V
CC
= 3.3V, CL = 50pF
V
CC
= 2.5V, CL = 30pF
V
CC
= 3.3V, CL = 50pF
TYPICAL
2.1
2.1
300
350
5.0
16
10
UNIT
ns
MHz
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type II
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
-40°C to +85°C
-40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16823 DL
74ALVCH16823 DGG
NORTH AMERICA
ACH16823 DL
ACH16823 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 Jul 29
2
853–2100 19800
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
PIN DESCRIPTION
PIN NUMBER
2, 27
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
56, 29
55, 30
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1OE, 2OE
1D0-1D8
2D0-2D8
1Q0-1Q8
2Q0-2Q8
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
V
CC
FUNCTION
Output enable input (active-Low)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
Positive supply voltage
PIN CONFIGURATION
1MR
1OE
1Q0
GND
1Q1
1Q2
V
CC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CP
1CE
1D0
GND
1D1
1D2
V
CC
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
LOGIC SYMBOL
1
28
2
27
1MR 2MR 1OE 2OE
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1CP 2CP 1CE 2CE
48
29
55
30
SW00341
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2CE
2CP
SH00014
1998 Jul 29
3
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
LOGIC SYMBOL (IEEE/IEC)
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2
1
55
56
27
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
8D
5, 6
∇
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
1, 2
∇
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
BUS HOLD CIRCUIT
V
CC
Data Input
To internal circuit
SW00044
SH00015
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
CP
CP
CP
CP
nD
CP
CP
CP
CP
CP
nD
nD
nD
nD
nD
nD
nD
nD
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
n = 1 or 2
SH00016
1998 Jul 29
4
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
H
h
L
l
X
Z
↑
=
=
=
=
=
=
=
nMR
L
H
H
H
H
nCE
X
L
L
L
H
nCP
X
↑
↑
L
X
nDx
X
h
l
X
X
OUTPUT
nQx
L
H
L
Q
0
Q
0
Disable outputs
Hold
Clear
Load and read data
OPERATING MODES
H
X
X
X
X
Z
HIGH voltage level
HIGH voltage level one set-up time prior to the Low-to-High clock transition
LOW voltage level
LOW voltage level one set-up time prior to the Low-to-High clock transition
Don’t care
HIGH impedance “off” state
LOW to High clock transition
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC supply voltage (for low-voltage applications)
for data input pins
V
I
V
O
T
amb
t
r
, t
f
DC Input voltage range
for control pins
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
0
0
–40
0
0
CONDITIONS
MIN
2.3
3.0
1.2
0
MAX
2.7
V
3.6
3.6
V
CC
5.5
V
CC
+85
20
10
V
V
V
V
°C
ns/V
UNIT
V
CC
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +5.5
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
850
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
京公网安备 11010802033920号
EEWORLD
