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DPS512S8PLL-70C

Description
SRAM Module, 512KX8, 70ns, CMOS, CDMA32, 0.600 INCH, DIP-32
Categorystorage    storage   
File Size542KB,6 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DPS512S8PLL-70C Overview

SRAM Module, 512KX8, 70ns, CMOS, CDMA32, 0.600 INCH, DIP-32

DPS512S8PLL-70C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerB&B Electronics Manufacturing Company
Parts packaging codeMODULE
package instructionDIP, DIP32,.6
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-CDMA-T32
JESD-609 codee0
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.00004 A
Minimum standby current2 V
Maximum slew rate0.08 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Base Number Matches1
4 Megabit CMOS SRAM
DPS512S8P/DPS512S8PL/DPS512S8PLL
DESCRIPTION:
The DPS512S8P/PL/PLL is a 512K X 8 high-density,
low-power static RAM module comprised of four
128K X 8 monolithic SRAM’s, an advanced
high-speed CMOS decoder and decoupling capacitors
surface mounted on a co-fired ceramic substrate
having side-brazed leads.
The DPS512S8P/PL/PLL is available in a 600-mil-wide,
32-pin dual-in-line package that conforms to the same
JEDEC standard pin configuration as the future four
megabit monolithics.
The DPS512S8P/PL/PLL operates from a single +5V
supply and all input and output pins are completely
TTL-compatible. The low standby power of the
DPS512S8P/PL/PLL makes it ideal for battery-backed
applications.
FEATURES:
524, 288 by 8 Bit Configuration
Access Times: 70*, 85, 100, 120, 150ns
Low Power Dissipation:
25
µ
W (typ.) Standby (DPS512S8PL/DPS512S8PLL)
40
µ
W (typ.) Standby (DPS512S8P)
375 mW (typ.) Operating
2-Volt Data Retention
Fully Static Operation - No Clock or Refresh
Required
All inputs and Outputs are TTL-Compatible
600 mil, 32-pin JEDEC Standard DIP Pinout
*
Available in Commercial only.
PIN NAMES
A0 - A18
Address Inputs
I/O0 - I/O7
Data In/Out
CE
Chip Enable
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
30A034-00
REV. E
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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