U62H64
Automotive Fast 8K x 8 SRAM
Features
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Fast 8192 x 8 bit static CMOS
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Description
The U62H64 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E1 and E2,
all inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
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RAM
35 ns Access Time
Bidirectional data inputs and data
outputs
Three-state outputs
Data retention mode at Vcc > 2V
Data retention current at 2 V:
< 3 µA (K-Type)
< 50 µA (A-Type)
Standby current
< 5 µA (K-Type)
< 100 µA (A-Type)
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
-40 to 85 °C
-40 to 125
°C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 200 mA
Package: SOP28 (300 mil)
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
SOP
Top View
April 20, 2004
1
U62H64
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
a
Symbol
V
CC
V
I
V
O
Min.
-0.3
-0.3
-0.3
-40
-40
-65
Max.
7
V
CC
+ 0.5
b
V
CC
+ 0.5
b
85
125
150
200
Unit
V
V
V
°C
°C
°C
mA
K-Type
A-Type
T
a
T
stg
|I
OS
|
b
c
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Power Supply Voltage
Data Retention Voltage
Input Low Voltage
d
Input High Voltage
d
Symbol
V
CC
V
CC(DR)
V
IL
V
IH
Conditions
Min.
4.5
2.0
-0.3
2.2
Max.
5.5
Unit
V
V
V
V
-
0.8
V
CC
+ 0.3
-2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns
April 20, 2004
3
U62H64
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
Conditions
= 5.5 V
= 0.8 V
= 2.2 V
= 35 ns
Min.
Max.
Unit
50
mA
Supply Current - Standby Mode
(CMOS level)
I
CC(SB)
= 5.5 V
V
CC
V
E1
= V
E2
= V
CC
- 0.2 V
K-Type
A-Type
= 5.5 V
V
CC
V
E1
= V
E2
= 2.2 V
= 2.0 V
V
CC(DR)
V
E1
= V
E2
= V
CC(DR)
- 0.2 V
K-Type
A-Type
V
CC
I
OH
V
CC
I
OL
V
CC
V
OH
V
CC
V
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
=
=
=
=
=
=
=
=
4.5 V
-4.0 mA
4.5 V
8.0 mA
4.5 V
2.4 V
4.5 V
0.4 V
2.4
-
-
8.0
-
-2
5
100
5
(typ. 2)
µA
µA
mA
Supply Current - Standby Mode
(TTL level)
Supply Current - Data Retention Mode
I
CC(SB)1
I
CC(DR)
3
50
-
0.4
-4.0
-
2
-
µA
µA
V
V
mA
mA
µA
µA
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input High Leakage Current
Input Low Leakage Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
OH
I
OL
I
IH
I
IL
= 5.5 V
= 5.5 V
= 5.5 V
=
0V
= 5.5 V
= 5.5 V
= 5.5 V
=
0V
I
OHZ
I
OLZ
-
-2
2
-
µA
µA
4
April 20, 2004
U62H64
Symbol
Switching Characteristics
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
Alt.
t
LZCE
t
LZOE
t
LZWE
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
t
PU
t
PD
IEC
t
en(E)
t
en(G)
t
en(W)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
0
35
20
25
0
25
20
15
0
0
5
15
15
12
Min.
Max.
Unit
5
0
0
35
35
35
15
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
V
CC
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
t
rec
2.2 V
E1
0V
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
0.8 V
t
DR
Data Retention
t
rec
0.8 V
E2
4.5 V
4.5 V
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
V
E1(DR)
≥
V
CC(DR)
- 0.2 V or V
E1(DR)
≤
0.2 V
V
E2(DR)
≤
0.2 V
Chip Deselect to Data Retention Time
Operating Recovery Time at V
CC(DR)
April 20, 2004
5
t
DR
:
t
rec
:
min 0 ns
min t
cR
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