AF4825P
P-Channel 30-V (D-S) MOSFET
Features
-Low r
DS(on)
Provides Higher Efficiency and Extends
Battery Life
-Miniature SO-8 Surface Mount Package Saves
Board Space
-High power and current handling capability
-Extended V
GS
range (±25) for battery pack
applications
General Description
These miniature surface mount MOSFETs utilize
High Cell Density process. Low r
DS(on)
assures
minimal power loss and conserves energy, making
this device ideal for use in power management
circuitry.
Typical applications are PWM DC-DC
converters, power management in portable and
battery-powered products such as computers,
printers, battery charger, telecommunication power
system, and telephones power system.
Product Summary
V
DS
(V)
-30
r
DS(on)
(mΩ)
13@V
GS
=-10V
19@V
GS
=-4.5V
I
D
(A)
-11.5
-9.3
Pin Assignments
S
S
S
G
1
2
3
4
8
7
6
5
Pin Descriptions
D
D
D
D
Pin Name
S
G
D
Description
Source
Gate
Drain
SOP-8
Ordering information
A X
Feature
F :MOSFET
PN
4825P X X X
Package
S: SOP-8
Lead Free
Blank : Normal
L : Lead Free Package
Packing
Blank : Tube or Bulk
A : Tape & Reel
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Jul 16, 2004
1/3
AF4825P
P-Channel 30-V (D-S) MOSFET
Absolute Maximum Ratings
(T
A
=25ºC unless otherwise noted)
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
(Note 1)
T
A
=25ºC
T
A
=70ºC
Pulsed Drain Current
(Note 2)
Continuous Source Current (Diode Conduction)
(Note 1)
T
A
=25ºC
Power Dissipation
(Note 1)
T
A
=70ºC
Operating Junction and Storage Temperature Range
Rating
-30
±25
-11.5
-9.3
±50
-2.1
3.1
2.3
-55 to 150
Units
V
V
A
A
A
W
ºC
Thermal Resistance Ratings
Symbol
R
θJC
R
θJA
Parameter
Maximum Junction-to-Case
(Note 1)
Maximum Junction-to-Ambient
(Note 1)
t
<
5 sec
t
<
5 sec
Maximum
25
50
Units
ºC/W
ºC/W
Note 1:
surface Mounted on 1”x 1” FR4 Board.
Note 2:
Pulse width limited by maximum junction temperature
Specifications
(T
A
=25ºC unless otherwise noted)
Symbol
Static
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
r
DS(on)
Parameter
Drain-Source breakdown Voltage
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
(Note 3)
Drain-Source On-Resistance
(Note 3)
Test Conditions
V
GS
=0V, I
D
=-250uA
V
DS
= V
GS
, I
D
=-250uA
V
DS
=0V, V
GS
=±25V
V
DS
=-24V, V
GS
=0V
V
DS
=-24V, V
GS
=0V,
T
J
=55ºC
V
DS
=-5V, V
GS
=-10V
V
GS
=-10V, I
D
=-11.5A
V
GS
=-4.5V, I
D
=-9.3A
V
GS
=-10V, I
D
=-13A,
T
J
=55ºC
V
GS
=-15V, I
D
=-11.5A
I
S
=2.5A, V
GS
=0V
V
DS
=-15V, V
GS
=-10V,
I
D
=-11.5A
Min.
-30
-1
-
-
-
-50
-
-
-
-
-
-
-
-
-
-
-
-
Limits
Typ.
-
-1.6
-
-
-
-
10
15
11
29
-0.8
64
11
17
15
13
100
54
Max.
-
-3
±100
-1
-5
-
13
19.0
13
-
-1.2
100
-
-
25
20
152
81
S
V
Unit
V
V
nA
uA
A
mΩ
g
fs
Forward Tranconductance
(Note 3)
V
SD
Diode Forward Voltage
Dynamic
(Note 4)
Q
g
Total Gate Charge
Q
gs
Gate-Source Charge
Q
gd
Gate-Drain Charge
Switching
t
d(on)
Turn-On Delay Time
t
r
Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Fall-Time
nC
V
DD
=-15, R
L
=6Ω,
ID=-1A, VGEN=-10V
nS
Note 3:
Pulse test: PW
<
300us duty cycle
<
2%.
Note 4:
Guaranteed by design, not subject to production testing.
Anachip Corp.
www.anachip.com.tw
2/3
Rev. 1.0 Jul 16, 2004
AF4825P
P-Channel 30-V (D-S) MOSFET
Marking Information
SOP-8L
( Top View )
8
Logo
Part Number
4825P
AA Y
W X
1
Lot code:
"X": Non-Lead Free; "X": Lead Free
"A~Z": 01~26;
"A~Z": 27~52
Week code:
"A~Z": 01~26;
"A~Z": 27~52
Year code:
"4" =2004
Factory code
~
Package Information
Package Type: SOP-8L
E
H
L
VIEW "A"
D
7 (4X)
0.015x45
7 (4X)
A2
A
A1
e
B
y
C
VIEW "A"
Symbol
A
A1
A2
B
C
D
E
e
H
L
y
θ
Dimensions In Millimeters
Min.
Nom.
Max.
1.40
1.60
1.75
0.10
-
0.25
1.30
1.45
1.50
0.33
0.41
0.51
0.19
0.20
0.25
4.80
5.05
5.30
3.70
3.90
4.10
-
1.27
-
5.79
5.99
6.20
0.38
0.71
1.27
-
-
0.10
O
0
-
8
O
Dimensions In Inches
Min.
Nom.
Max.
0.055
0.063
0.069
0.040
-
0.100
0.051
0.057
0.059
0.013
0.016
0.020
0.0075
0.008
0.010
0.189
0.199
0.209
0.146
0.154
0.161
-
0.050
-
0.228
0.236
0.244
0.015
0.028
0.050
-
-
0.004
O
0
-
8
O
Anachip Corp.
www.anachip.com.tw
3/3
Rev. 1.0 Jul 16, 2004
FPGA/CPLD
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