featuring individual input and output registers with clocked D-type flip-flop,
- 16 x 16 parallel multiplier-accumulator with selectable accumulation and a preload capability which enables input data to be preloaded into the output
registers, individual three-state output ports for the Extended Product (XTP)
subtraction
and Most Significant Product (MSP) and a Least Significant Product output
- High-speed: 20ns multiply-accumulate time
- IDT7210 features selectable accumulation, subtraction, rounding and (LSP) which is multiplexed with the Y input.
preloading with 35-bit result
The X
IN
and Y
IN
data input registers may be specified through the use
- IDT7210 is pin and function compatible with the TRW TDC1010J, TMC2210, of the Two’s Complement input (TC) as either a two’s complement or an
Cypress CY7C510, and AMD AM29510
unsigned magnitude, yielding a full-precision 32-bit result that may be
- Performs subtraction and double precision addition and multiplication
accumulated to a full 35-bit result. The three output registers – Extended
- Produced using advanced CMOS high-performance technology
Product (XTP), Most Most Significant Product (MSP) and Least Significant
- TTL-compatible
Product (LSP) – are controlled by the respective TSX, TSM and TSL input
- Available in PLCC
lines. The LSP output can be routed through Y
IN
ports.
- Speeds available: L20/25/35/45/55/65
Accumulate input (ACC) enables the device to perform either a multiply
or a multiply-accumulate function. In the multiply-accumulate mode, output
DESCRIPTION:
data can be added to or subtracted from previous results. When the
Subtraction (SUB) input is active simultaneously with an active ACC, a
The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplier-
subtraction can be performed. The double precision accumulated result is
accumulator that is ideally suited for real-time digital signal processing
rounded down to either a single precision or single precision plus 3-bit
applications. Fabricated using CMOS silicon gate technology, this device
offers a very low-power alternative to existing bipolar and NMOS counterparts, extended result. In the multiply mode, the Extended Product output (XTP)
with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns is sign extended in the two’s complement mode or set to zero in the unsigned
mode. The Round (RND) control rounds up the Most Significant Product
maximum) performance.
(MSP) and the 3-bit Extended Product (XTP) outputs. When Preload input
A pin and functional replacement for TRW’s TDC1010J, the IDT7210 (PREL) is active, all the output buffers are forced into a high-impedance state
operates from a single 5 volt supply and is compatible with standard TTL (see Preload truth table) and external data can be loaded into the output
logic levels. The architecture of the IDT7210 is fairly straightforward, register by using the TSX, TSL and TSM signals as input controls.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
CLKX
X
IN
(X
15
- X
0
)
16
ACC, SUB,
RND, TC
4
Y
IN
CLKY (Y
15
- Y
0
/P
15
- P
0
)
16
XREGISTER
CONTROL
REGISTER
YREGISTER
MULTIPLIER ARRAY
32 +
TSL
PREL
+/–
ACCUM ULATOR
16
35
35
CLKP
XTMP R EGISTER
3
MSP REGISTER
LSP REGISTER
TSX
PREL
3
16
TSM
XTP
OUT
(P
34
- P
32
)
MSP
OUT
(P
31
- P
16
)
COMMERCIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
APRIL 2001
DSC-2018/-
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
P
10,
Y
10
P
11,
Y
11
P
12,
Y
12
P
13,
Y
13
P
14,
Y
14
P
15,
Y
15
45
P
2,
Y
2
P
3,
Y
3
P
4,
Y
4
P
5,
Y
5
P
6,
Y
6
P
7,
Y
7
P
8,
Y
8
P
9,
Y
9
GND
GND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
P
1,
Y
1 61
P
0,
Y
0 62
X
0 63
X
1 64
X
2 65
X
3 66
X
4 67
X
5 68
X
6 1
X
7 2
X
8 3
X
9 4
X
10 5
X
11 6
X
12 7
X
13 8
X
14 9
J68-1
P
16
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P
17
P
18
P
19
P
20
P
21
P
22
P
23
P
24
P
25
P
26
P
27
P
28
P
29
P
30
P
31
P
32
P
33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X
15
TSX
PR EL
ACC
CLKX
CLKY
PLCC
TOP VIEW
2
CLKP
SUB
RND
TSM
TSL
Vcc
Vcc
Vcc
Vcc
P
34
TC
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
X
0
-
15
Y
0 - 15
/ P
0
-
15
P
16
-
31
P
32
-
34
CLKX
CLKY
CLKP
TSX
TSM
TSL
PREL
ACC
I/O
I
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Data Inputs
Multiplexed I/O port. Y
0 - 15
are data inputs and can be used to preload LSP register on PREL = 1. P
0
-
15
are LSP register outputs -
enabled by TSL.
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when PREL = 1.
Input data X
0
-
15
loaded in X input register on CLKX rising edge.
Input data Y
0 - 15
loaded in Y input register on CLKY rising edge.
Output data loaded into output register on rising edge of CLKP.
TSX = 0 enables XTP outputs, TSX = 1 tristates P
32
-
34
lines.
TSM = 0 enables MSP outputs, TSM = 1 tristates P
16
-
31
lines.
TSL = 0 enables LSP outputs, TSL = 1 tristates P
0
-
15
lines.
When PREL= 1 data is input on P
0
-
15
lines. When PREL = 0, inputs on these lines are ignored.
This input is loaded into the control register on the rising edge of (CLKX + CLKY). When ACC = 1 and SUB = 0 an accumulate
operation is performed. When ACC = 1 and SUB = 1, a subtract operation is performed. When ACC = 0, the SUB input is a don't
care and the device acts as a simple multipler with no accumulation
This input is loaded into the control register on the rising edge of (CLKX + CLKY). This input is active only when ACC = 1. When SUB
= 1 the contents of the output register are subtracted from the result and stored back in the output register. When SUB = 0 the
contents of the output register are added to the result and stored back in the output register.
This input is loaded into the control register on the rising edge of (CLKX + CLKY). When TC = 1, the X and Y input are assumed to be
in two's complement form. When TC = 0, X and Y inputs are assumed to be in unsigned magnitude form.
This input is loaded into the control register on the rising edge of (CLKX + CLKY). RND is inactive when low. RND = 1, adds a "1" to
the most significant bit of the LSP, to round MSP and XTP data
Description
SUB
I
TC
RND
I
I
3
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PRELOAD TRUTH TABLE
PREL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TSX
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TSM
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TSL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XTP
Q
Q
Q
Q
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PL
PL
PL
PL
MSP
Q
Q
Hi-Z
Hi-Z
Q
Q
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PL
PL
Hi-Z
Hi-Z
PL
PL
LSP
Q
Hi-Z
Q
Hi-Z
Q
Hi-Z
Q
Hi-Z
Hi-Z
PL
Hi-Z
PL
Hi-Z
PL
Hi-Z
PL
NOTES ON TWO'S COMPLEMENT
FORMATS
1. In two's complement notation, the location of the binary point that signifies
the separation of the fractional and integer fileds is just after the sign,
between the sign bit (-2
0
) and the next significant bit for the multiplier
inputs. This same format is carried over to the output format, except that
the extended significance of the integer filed is provided to extend the
utility of the accumulator. In the case of the output rotation, the output
binary point is located between the2
0
and 2
1
bit positions. The location
of the binary point is arbitrary, as long as there is consistency with both
the input and output formats. The number filed can be considered
entirely integer with the binary point just to the right of the least significant
bit for the input, product and the accumulated sum.
2. When in the non-accumulating mode, the first four bits (P
34
to P
31
) will all
indicate the sign of the product. Additionally, the P
30
term will also indicate
the sign with one exception, when multiplying -1 x -1. With the additional
bits that are available in this multiplier, the –1 x –1 is a valid operation
that yields a +1 product.
3. In operations that require the accumulation of single products or sum of
products, there is no change in format. To allow for a valid summation
beyond that available for a single multiplication product, three additional
significant bits (guard bits) are provided. This is the same as if the product
was accumulated off-chip in a separate 35-bit wide adder. Taking the
sign at the most significant bit position will guarantee that the largest
number field will be used. When the accumulated sum only occupies the
right hand portion of the accumulator, the sign will be extended into the
lesser significant bit positions.
NOTES:
Hi Z = Output buffers at high-impedance (output disabled)
Q = Output buffers at low impedance. Contents of output register will be
transferred to output pins.
PL = Output buffers at high-impedance or output disabled. Preload data
supplied externally at output pins will be loaded into the output
register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Power Supply Voltage
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+ 0.5
0 to +70
–55 to +125
–55 to +125
50
Unit
V
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
NOTE:
1. This parameter is sampled and not 100% tested.
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, Vcc = 5V ± 10%
Symbol
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL(4)
I
OS
I
CC(2)
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Operating Power Supply Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
IN
= 0V to
V
CC
V
CC
= Max., Outputs Disabled
V
OUT
= 0 to
V
CC
V
CC
= Min., I
OH
= –2mA
V
CC
= Min., I
OL
= 4mA
V
CC
= Max., V
O
GND
V
CC
= Max., Outputs Enabled
f = 10MHz
(2)
C
L
= 50 pF
V
IN
≥
V
IH
, V
IN
≤
V
IL
V
IN
≥
V
CC
–0.2V, V
IN
≤
0.2V
V
CC
= Max., Outputs Disabled
Min.
2
—
—
—
2.4
—
-20
—
Typ.
(1)
—
—
—
—
—
—
—
45
Max.
—
0.8
10
10
—
0.4
-100
90
Unit
V
V
µA
µA
V
V
mA
mA
I
CCQ1
I
CCQ2
I
CC
/f
(2,3)
Quiescent Power Supply Current
Quiescent Power Supply Current
Increase in Power Supply
Current MHz
—
—
—
20
4
—
30
10
6
mA
mA
mA/
MHz
NOTES:
1. Typical implies V
CC
= 5V and T
A
= +25°C.
2. I
CC
is measured at 10MHz and V
IN
= 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
I
CC
= 90+ 6(f –10)mA, where f = operating frequency in MHz.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. I
OL
= 4mA for t
MA
> 55ns.
5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, Vcc = 5V ± 10%
Symbol
t
MA
t
D
t
ENA
t
DIS
t
S
t
H
t
PW
t
HCL
Parameter
Multiply-Accumulate Time
(2)
Output Delay
(2)
3-State Enable Time
3-State Disable Time
(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
Relative Hold Time
7210L20
7210L25
7210L35
7210L45
7210L55
7210L65
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
20
2
25
2
35
2
45
2
55
2
65
2
18
2
20
2
25
2
25
2
30
2
35
—
18
–
20
–
25
–
25
–
30
–
30
—
18
–
20
–
25
–
25
–
30
–
30
10
—
12
–
12
–
15
–
20
–
25
–
3
—
3
–
3
–
3
–
3
–
3
–
9
—
10
–
10
–
15
–
20
–
25
–
0
—
0
–
0
–
0
–
0
–
0
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition is measured ±500mV from steady state voltage.
京公网安备 11010802033920号
EEWORLD
