HM5118165 Series
16 M EDO DRAM (1-Mword
×
16-bit)
1 k Refresh
ADE-203-636D (Z)
Rev. 4.0
Nov. 1997
Description
The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word
×
16-bit. It employs the
most advanced 0.5
µm
CMOS technology for high performance and low power. The HM5118165 offers
Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ
and 50-pin plastic TSOP II.
Features
•
Single 5 V (±10%)
•
Access time : 50 ns/60 ns/70 ns (max)
•
Power dissipation
Active mode : 1045 mW/935 mW/825 mW (max)
Standby mode : 11 mW (max)
: 0.83 mW (max) (L-version)
•
EDO page mode capability
•
Refresh cycles
1024 refresh cycles : 16 ms
: 128 ms (L-version)
•
4 variations of refresh
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
Self refresh (L-version)
•
2CAS-byte control
•
Battery backup operation (L-version)
HM5118165 Series
Ordering Information
Type No.
HM5118165J-5
HM5118165J-6
HM5118165J-7
HM5118165LJ-5
HM5118165LJ-6
HM5118165LJ-7
HM5118165TT-5
HM5118165TT-6
HM5118165TT-7
HM5118165LTT-5
HM5118165LTT-6
HM5118165LTT-7
Access time
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50/44DC)
Package
400-mil 42-pin plastic SOJ (CP-42D)
2
HM5118165 Series
Pin Arrangement
HM5118165J/LJ Series
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
(Top view)
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
HM5118165TT/LTT Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(Top view)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Pin Description
Pin name
A0 to A9
Function
Address input
— Row/Refresh address A0 to A9
— Column address
A0 to A9
Data input/Data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
Power supply
Ground
No connection
I/O0 to I/O15
RAS
UCAS, LCAS
WE
OE
V
CC
V
SS
NC
3
HM5118165 Series
Block Diagram
RAS
UCAS LCAS
WE
OE
Timing and control
A0
A1
to
A9
Row decoder
•
•
•
Column
address
buffers
Column decoder
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
•
•
•
I/O buffers
Row
address
buffers
I/O0
to
I/O15
4
HM5118165 Series
Truth Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
H
L
L
L
UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
WE
D
H
H
H
L
*2
L*
2
L*
2
L*
2
L*
2
L*
2
H to L
H to L
H to L
D
D
D
D
H
OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
H
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Open
Operation
Standby
Lower byte Read cycle
Upper byte
Word
Lower byte Early write cycle
Upper byte
Word
Lower byte Delayed write cycle
Upper byte
Word
Lower byte Read-modify-write cycle
Upper byte
Word
Word
Word
Word
Word
Read cycle (Output disabled)
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle or
Self refresh cycle (L-version)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t
WCS
≥
0 ns Early write cycle
t
WCS
< 0 ns Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS.
(Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.)
However write OPERATION and output High-Z control are done independently by each
UCAS,
LCAS.
ex. if
RAS
= H to L,
UCAS
= H,
LCAS
= L, then
CAS-before-RAS
refresh cycle is selected.
5
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