Integrated
Circuit
Systems, Inc.
ICSSSTUB32872A
Advance Information
28-Bit Registered Buffer for DDR2
Recommended Application:
•
DDR2 Memory Modules
•
Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
•
Optimized for DDR2 400/533/667 JEDEC 4 Rank
VLP DIMMS
Product Features:
•
28-bit 1:1 registered buffer with parity check
functionality
•
Supports SSTL_18 JEDEC specification on data
inputs and outputs
•
Supports LVCMOS switching levels on RESET input
•
50% more dynamic driver strength than standard
SSTU32864
•
Low voltage operation
V
DD
= 1.7V to 1.9V
•
Available in 96 BGA package
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
2
3
4
5
6
96 Ball BGA
(Top View)
Functionality Truth Table
In puts
RESET
H
H
H
H
H
H
H
H
H
H
H
H
L
DCS0
L
L
L
L
L
L
H
H
H
H
H
H
X or
floating
DCS1
L
L
L
H
H
H
L
L
L
H
H
H
X or
floating
CK
↑
↑
L or H
↑
↑
L or H
↑
↑
L or H
↑
↑
L or H
X or
floating
CK
↓
↓
L or H
↓
↓
L or H
↓
↓
L or H
↓
↓
L or H
X or
floating
Dn,
DODTn,
DCK En
L
H
X
L
H
X
L
H
X
L
H
X
X or
floating
Qn
L
H
Q
0
L
H
Q
0
L
H
Q
0
Q
0
Q
0
Q
0
L
Outputs
QCS
L
L
Q
0
L
L
Q
0
H
H
Q
0
H
H
Q
0
L
QODT,
QCKE
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
1222F—3/13/07
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICSSSTUB32872A
Advance Information
General Description
This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V V
DD
operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are
LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.
The
ICSSSTUB32872A
operates from a differential clock (CK and CK). Data are registered at the crossing of CK
going high, and CK going low.
The device supports low-power standby operation. When the reset input (RESET) is low, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are
allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced
low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held
in the low state during power up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK
and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs are low, and the
clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully
enabled, the design of the
ICSSSTUB32872A
must ensure that the outputs will remain low, thus ensuring no
glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when
both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function
normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs
low and the PTYERR output high.
The
ICSSSTU32872A
includes a parity checking function. The
ICSSSTUB32872A
accepts a parity bit from the
memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
Inputs
RESET
H
H
H
H
H
H
H
H
H
H
L
DCS0
L
L
L
L
H
H
H
H
H
X
X or
floating
DCS1
H
H
H
H
L
L
L
L
H
X
X or
floating
CK
↑
↑
↑
↑
↑
↑
↑
↑
↑
L or H
X or
floating
CK
↓
↓
↓
↓
↓
↓
↓
↓
↓
L or H
X or
floating
of inputs = H
(D0-D21)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
X
X or floating
PARIN*
L
L
H
H
L
L
H
H
X
X
X or
floating
Output
PTYERR**
H
L
L
H
H
L
L
H
PTYERR
0
PTYERR
0
H
*
PARIN arrives one clock cycle after the data to which it applies.
** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR
is low, it stays latched low for two clock cycles or until RESET is driven low.
1222F—3/13/07
3
ICSSSTUB32872A
Advance Information
Ball Assignment
Signal Group
Signal Name
Type
Description
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
low when a valid address/command is present. The register
can be programmed to re-drive all D-inputs when at least
one Chip Slect input is LOW.
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Ungated inputs DCKE0, DCKE1, SSTL_18
DODT0, DODT1
Chip Select
gated inputs
Chip Select
inputs
D0 ... D21
DCS0 , DCS1
SSTL_18
SSTL_18
Re-driven
outputs
Q0...Q21,
QCS0-1,
QCKE0-1,
QODT0-1
PARIN
SSTL_18
Parity input
SSTL_18
Input parity is received on pin PARIN and should maintain
odd parity across the D0...D20 inputs, at the rising edge of the
clock.
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by
an additional clock cycle for compatibility with final parity
out timing on the industry-standard DDR-II register with
parity (in JEDEC definition).
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET
also resets the PTYERR signal.
Parity error
output
PTYERR
Open drain
Clock inputs
CK, CK
SSTL_18
Miscellaneous
inputs
RESET
1.8 V
LVCMOS
VREF
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
1222F—3/13/07
4
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