HM6264B Series
64 k SRAM (8-kword
×
8-bit)
ADE-203-454B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HM6264B is 64k-bit static RAM organized 8-kword
×
8-bit. It realizes higher performance
and low power consumption by 1.5
µm
CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density
mounting.
Features
•
High speed
Fast access time: 85/100 ns (max)
•
Low power
Standby: 10
µW
(typ)
Operation: 15 mW (typ) (f = 1 MHz)
•
Single 5 V supply
•
Completely static memory
No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output
Three state output
•
Directly TTL compatible
All inputs and outputs
•
Battery backup operation capability
HM6264B Series
Ordering Information
Type No.
HM6264BLP-8L
HM6264BLP-10L
HM6264BLSP-8L
HM6264BLSP-10L
HM6264BLFP-8LT
HM6264BLFP-10LT
Access time
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
Package
600-mil, 28-pin plastic DIP (DP-28)
300-mil, 28-pin plastic DIP(DP-28N)
450-mil, 28-pin plastic SOP(FP-28DA)
Pin Arrangement
HM6264BLP/BLSP/BLFP Series
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
(Top view)
Pin Description
Pin name
A0 to A12
I/O1 to I/O8
CS1
CS2
Function
Address input
Data input/output
Chip select 1
Chip select 2
Pin name
WE
OE
NC
V
CC
V
SS
Function
Write enable
Output enable
No connection
Power supply
Ground
HM6264B Series
Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
I/O1
Input
data
control
I/O8
Row
decoder
Memory array
256
×
256
V
CC
V
SS
Column I/O
Column decoder
A1 A2 A0 A10 A3
CS2
CS1
Timing pulse generator
Read, Write control
WE
OE
HM6264B Series
Function Table
WE
×
×
H
H
L
L
CS1
H
×
L
L
L
L
CS2
×
L
H
H
H
H
OE
×
×
H
L
H
L
Mode
Not selected (power down)
Not selected (power down)
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
I/O pin
High-Z
High-Z
High-Z
Dout
Din
Din
Ref. cycle
—
—
—
Read cycle (1)–(3)
Write cycle (1)
Write cycle (2)
Note:
×:
H or L
Absolute Maximum Ratings
Parameter
Power supply voltage
*1
Terminal voltage
*1
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +7.0
–0.5
*2
to V
CC
+ 0.3
*3
1.0
0 to + 70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
Notes: 1. Relative to V
SS
2. V
T
min: –3.0 V for pulse half-width
≤
50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Note:
V
IH
V
IL
Min
4.5
0
2.2
–0.3
*1
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
1. V
IL
min: –3.0 V for pulse half-width
≤
50 ns
HM6264B Series
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5 V
±10%,
V
SS
= 0 V)
Parameter
Input leakage current
Output leakage current
Operating power supply
current
Average operating power
supply current
Symbol Min
|I
LI
|
|I
LO
|
I
CCDC
I
CC1
—
—
—
—
Typ
*1
Max
—
—
7
30
2
2
15
45
Unit
µA
µA
mA
mA
Test conditions
Vin = V
SS
to V
CC
CS1
= V
IH
or CS2 = V
IL
or
OE
= V
IH
or
WE
= V
IL
, V
I/O
= V
SS
to V
CC
CS1
= V
IL
, CS2 = V
IH
, I
I/O
= 0 mA
others = V
IH
/V
IL
Min cycle, duty = 100%,
CS1
= V
IL
, CS2 = V
IH
, I
I/O
= 0 mA
others = V
IH
/V
IL
Cycle time = 1
µs,
duty = 100%, I
I/O
= 0 mA
CS1
≤
0.2 V, CS2
≥
V
CC
– 0.2 V,
V
IH
≥
V
CC
– 0.2 V, V
IL
≤
0.2 V
CS1
= V
IH
, CS2 = V
IL
CS1
≥
V
CC
– 0.2 V, CS2
≥
V
CC
– 0.2 V or
0 V
≤
CS2
≤
0.2 V, 0 V
≤
Vin
I
OL
= 2.1 mA
I
OH
= –1.0 mA
I
CC2
—
3
5
mA
Standby power supply
current
I
SB
I
SB1
—
—
—
2.4
1
2
—
—
3
50
0.4
—
mA
µA
V
V
Output low voltage
Output high voltage
V
OL
V
OH
Notes: 1. Typical values are at V
CC
= 5.0 V, Ta = +25°C and not guaranteed.
Capacitance
(Ta = 25°C, f = 1.0 MHz)
Parameter
Input capacitance
*1
Input/output capacitance
*1
Note:
Symbol
Cin
C
I/O
Min
—
—
Typ
—
—
Max
5
7
Unit
pF
pF
Test conditions
Vin = 0 V
V
I/O
= 0 V
1. This parameter is sampled and not 100% tested.