HM62V8512CLTT-5SL datasheet, PDF

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HM62V8512CLTT-5SL: Description4 M SRAM (512-kword x 8-bit); Categorystorage storage; File Size81KB，16 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HM62V8512CLTT-5SL Overview

4 M SRAM (512-kword x 8-bit)

HM62V8512CLTT-5SL Parametric

Parameter Name	Attribute value
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP32,.46
Contacts	32
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	55 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
length	20.95 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP32,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.00002 A
Minimum standby current	2.7 V
Maximum slew rate	0.025 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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HM62V8512C Series

4 M SRAM (512-kword

8-bit)

ADE-203-1210A (Z)

Rev. 1.0

Jan. 31, 2001

Description

The Hitachi HM62V8512C is a 4-Mbit static RAM organized 512-kword

8-bit. It realizes higher density,

higher performance and low power consumption by employing CMOS process technology (6-transistor

memory cell). The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is

available for high density mounting. The HM62V8512C is suitable for battery backup system.

Features

•

Single 3.0 V supply: 2.7 V to 3.6 V

•

Access time: 55/70 ns (max)

•

Power dissipation



Active: 6.0 mW/MHz (typ)



Standby: 2.4 µW (typ)

•

Completely static memory. No clock or timing strobe required

•

Equal access and cycle times

•

Common data input and output: Three state output

•

Directly LV-TTL compatible: All inputs

•

Battery backup operation

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