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HM658512ALTT-8V

Description
4 M PSRAM (512-kword x 8-bit) 2 k Refresh
Categorystorage    storage   
File Size107KB,22 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HM658512ALTT-8V Overview

4 M PSRAM (512-kword x 8-bit) 2 k Refresh

HM658512ALTT-8V Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
Parts packaging codeTSOP
package instructionTSOP2, TSOP32,.46
Contacts32
Reach Compliance Codeunknow
Maximum access time80 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length20.95 mm
memory density4194304 bi
Memory IC TypePSEUDO STATIC RAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP32,.46
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum standby current0.00005 A
Minimum standby current3 V
Maximum slew rate0.075 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width10.16 mm
HM658512A Series
4 M PSRAM (512-kword
×
8-bit)
2 k Refresh
ADE-203-218C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword
×
8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8
×
20 mm TSOP with thickness
of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.
Features
Single 5 V (±10%)
High speed
Access time
CE
access time: 70/80/100 ns (max)
Cycle time
Random read/write cycle time:
115/130/160 ns (min)
Low power
Active: 250 mW (typ)
Standby: 200 µW (typ)
Directly TTL compatible
All inputs and outputs
Simple address configuration
Non multiplexed address
Refresh cycle
2048 refresh cycles: 32 ms

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