INTEGRATED CIRCUITS
PCA9554/PCA9554A
8-bit I
2
C and SMBus I/O port with interrupt
Product data
Supersedes data of 2002 May 13
2002 Jul 26
Philips
Semiconductors
Philips Semiconductors
Product data
8-bit I
2
C and SMBus I/O port with interrupt
PCA9554/PCA9554A
DESCRIPTION
The PCA9554 and PCA9554A are 16-pin CMOS devices that
provide 8 bits of General Purpose parallel Input/Output (GPIO)
expansion for I
2
C/SMBus applications and were developed to
enhance the Philips family of I@C I/O expanders. The improvements
include higher drive capability, 5V I/O tolerance, lower supply
current, individual I/O configuration, 400 kHz clock frequency, and
smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors,
pushbuttons, LEDs, fans, etc..
FEATURES
•
Operating power supply voltage range of 2.3 to 5.5 V
•
5 V tolerant I/Os
•
Polarity inversion register
•
Active low interrupt output
•
Low stand-by current
•
Noise filter on SCL/SDA inputs
•
No glitch on power-up
•
Internal power-on reset
•
8 I/O pins which default to 8 inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Four packages offered: SO16, SSOP16, TSSOP16, and
HVQFN16
exceeds 100 mA
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
The PCA9554/54A consist of an 8-bit Configuration register (Input or
Output selection); 8-bit Input register, 8-bit Output register and an
8-bit Polarity inversion register (Active high or Active low operation).
The system master can enable the I/Os as either inputs or outputs
by writing to the I/O configuration bits. The data for each Input or
Output is kept in the corresponding Input or Output register. The
polarity of the read register can be inverted with the Polarity
Inversion Register. All registers can be read by the system master.
Although pin to pin and I
2
C address compatible with the PCF8574
series, software changes are required due to the enhancements and
are discussed in Application Note AN469.
The PCA9554/54A open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C address and
allow up to eight devices to share the same I
2
C/SMBus. The
PCA9554A is identical to the PCA9554 except that the fixed I
2
C
address is different allowing up to sixteen of these devices (eight of
each) on the same I
2
C/SMBus.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO (wide)
16-Pin Plastic SSOP
16-Pin Plastic TSSOP
16-Pin Plastic HVQFN
16-Pin Plastic SO (wide)
16-Pin Plastic SSOP
16-Pin Plastic TSSOP
TEMPERATURE
RANGE
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
ORDER CODE
PCA9554D
PCA9554DB
PCA9554PW
PCA9554BS
PCA9554AD
PCA9554ADB
PCA9554APW
TOPSIDE MARK
PCA9554D
9554DB
9554DH
9554
PCA9554AD
9554A
9554ADH
DRAWING NUMBER
SOT162-1
SOT338-1
SOT403-1
SOT629-1
SOT162-1
SOT338-1
SOT403-1
SOT629-1
16-Pin Plastic HVQFN
–40 to +85
°C
PCA9554ABS
554A
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
2002 Jul 26
2
853-2243 28672
Philips Semiconductors
Product data
8-bit I
2
C and SMBus I/O port with interrupt
PCA9554/PCA9554A
PIN CONFIGURATION — SO, SSOP, TSSOP
A0 1
A1
2
16 V
DD
15 SDA
14 SCL
13 INT
12 I/O7
11 I/O6
10 I/O5
9
I/O4
PIN CONFIGURATION — HVQFN
A1
16
A0
15
V
DD
14
SDA
13
12 SCL
11 INT
10 I/O7
9
5
6
7
8
I/O6
I/O5
A2
I/O0
I/O1
I/O2
1
2
3
4
A2 3
I/O0 4
I/O1 5
I/O2 6
I/O3 7
V
SS
8
I/O3
V
SS
I/O4
su01410
Figure 1. Pin configuration — SO, SSOP, TSSOP
TOP VIEW
su01670
Figure 2. Pin Configuration — HVQFN
PIN DESCRIPTION
SO. SSOP,
TSSOP PIN
NUMBER
1
2
3
4–7
8
9
13
14
15
16
HVQFN
PIN
NUMBER
15
16
1
2–5
6
7–10
11
12
13
14
SYMBOL
A0
A1
A2
I/O0–3
V
SS
I/O4–7
INT
SCL
SDA
V
DD
FUNCTION
Address input 0
Address input 1
Address input 2
I/O0 to I/O3
Supply ground
I/O4 to I/O7
Interrupt output (open drain)
Serial clock line
Serial data line
Supply voltage
BLOCK DIAGRAM
A0
A1
A2
SCL
SDA
INPUT
FILTER
I
2
C/SMBUS
CONTROL
8-BIT
INPUT/
OUTPUT
PORTS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
V
DD
POWER-ON
RESET
V
SS
LP
FILTER
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
INT
V
CC
WRITE pulse
READ pulse
SU01411
Figure 3. Block diagram
2002 Jul 26
3
Philips Semiconductors
Product data
8-bit I
2
C and SMBus I/O port with interrupt
PCA9554/PCA9554A
REGISTERS
Command Byte
Command
0
1
2
3
Protocol
Read byte
Read/write byte
Read/write byte
Read/write byte
Function
Input port register
Output port register
Polarity inversion register
Configuration register
Register 2 – Polarity Inversion Register
bit
default
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
N0
0
This register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with ‘1’), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a ‘0’), the Input Port data polarity is retained.
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 3 – Configuration Register
bit
default
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
Register 0 – Input Port Register
bit
default
I7
1
I6
1
I5
1
I4
1
I3
1
I2
1
I1
1
I0
1
This register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to V
DD
.
Power-on Reset
When power is applied to V
DD
, an internal power-on reset holds the
PCA9554 in a reset state until V
DD
has reached V
POR
. At that point,
the reset condition is released and the PCA9554 registers and state
machine will initialize to their default states.
Register 1 – Output Port Register
bit
default
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
This register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.
Interrupt Output
The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the input port register.
2002 Jul 26
4
Philips Semiconductors
Product data
8-bit I
2
C and SMBus I/O port with interrupt
PCA9554/PCA9554A
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
FF
WRITE
CONFIGURATION
PULSE
WRITE PULSE
C
K
Q
D
FF
I/O0 TO I/O7
C
K
Q
Q2
Q
Q
Q1
100 kΩ
OUTPUT PORT
REGISTER DATA
V
DD
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
TO INT
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SU01472
NOTE:
At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up (100 kΩ typ.) to
V
DD
. The input voltage may be raised above V
DD
to a maximum of
5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either V
DD
or V
SS
.
2002 Jul 26
5
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