®
M34S32
PRELIMINARY DATA
32K Serial I
2
C Bus EEPROM
With User-Defined Read-Only Block and 32-Byte OTP Page
s
TWO WIRE I
2
C SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
COMPATIBLE WITH I
2
C EXTENDED
ADDRESSING
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
HARDWARE WRITE CONTROL
USER-DEFINED READ-ONLY BLOCK
32 BYTES OTP PAGE
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD and LATCH-UP
PERFORMANCES
Figure 1. Delivery Forms
s
s
s
s
s
s
s
s
s
8
8
1
1
PSDIP8 (BN)
0.25 mm Frame
S08 (MN)
150 mil Width
s
s
s
Figure 2. Logic Diagram
DESCRIPTION
The M34S32 is a 32K bit electrically erasable pro-
grammable memory (EEPROM), organized as
4096 x 8 bits.
Table 1. Signal Names
SDA
SCL
WC
WCR
V
CC
V
SS
Serial Data Address Input/Output
Serial Clock
Write Control
Write Control of Control Register
Supply Voltage
Ground
VCC
SCL
WC
WCR
M34S32
SDA
VSS
AI02468
June 1998
This is a Preliminary Data. Details are subject to change without notice.
1/18
M34S32
Figure 3. DIP Pin Connections
Figure 4. SO Pin Connections
M34S32
NC
NC
WCR
VSS
1
2
3
4
8
7
6
5
AI02448
M34S32
VCC
WC
SCL
SDA
NC
NC
WCR
VSS
1
2
3
4
8
7
6
5
AI02449
VCC
WC
SCL
SDA
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
T
LEAD
(SO8 package)
(PSDIP8
package)
Input or Output Voltages
Supply Voltage
(Human Body model)
Electrostatic Discharge Voltage
V
ESD
Electrostatic Discharge Voltage
1. MIL-STD-883C, 3015.7 (100 pF,
1500
Ω)
Parameter
Value
–40 to 125
–65 to 150
40 sec
10 sec
215
260
–0.6 to 6.5
–0.3 to 6.5
4000
Unit
°C
°C
°C
°C
V
V
V
V
IO
V
CC
(Machine model)
2. EIAJ IC-121
(200 pF, 0
Ω)
(Condition
C)
500
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2/18
M34S32
DESCRIPTION (cont’d)
The memory is compatible with the I
2
C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The memory carries a built-in 4 bit, unique
device identification code (1010) corresponding to
the I
2
C bus definition. The memory behaves as
slave devices in the I
2
C protocol with all memory
operations synchronized by the serial clock. Read
and write operations are initiated by a START con-
dition generated by the bus master. The START
condition is followed by the Device Select Byte.
This is a stream of 4 bits (the identification code
1010), then 3 bits of memory block access input,
plus one read/write bit. The byte is finally terminat-
ed by an acknowledge bit.
The M34S32 contains three memory blocks: the
OTP page, the EEPROM block and the ROM
block. The OTP (One Time Programmable) page
is a page of 32 bytes, written once by the user. The
OTP page is not located within the 32 Kbits EEP-
ROM area. Once written, the OTP page cannot be
modified by further write instructions. The ROM
block resides inside the 32 Kbit EEPROM area.
The size of the ROM block is defined (by the user)
with the help of the Control Register.
The OTP page is accessed with the Device Select
Byte 1010001x, the EEPROM and ROM blocks
are accessed with the Device Select Byte
1010000x. The control register is accessed with
the Device Select Byte 1010100x (see Table 3).
Table 3. Device Select Byte
Device Code
Device Select Bit
EEPROM and ROM access
OTP Page access
Control Register access
b7
1
1
1
b6
0
0
0
b5
1
1
1
b4
0
0
0
Memory Block Access
b3
0
0
1
b2
0
0
0
b1
0
1
0
RW
b0
RW
RW
RW
When writing data to the memory it responds to
the 8 bits received by asserting an acknowledge
bit during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the
data bytes in the same way.
Data transfers are terminated with a STOP condi-
tion.
Power On Reset: VCC lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold val-
ue, all operations are disabled and the device will
not respond to any command. A stable VCC must
be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to
VCC to act as a pull up (see Figure 3)
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memo-
ry. It is an open drain output that may be wire-
OR’ed with other open drain or open collector sig-
nals on the bus. A pull-up resistor must be con-
nected from the SDA bus line to V
CC
(see Figure
3).
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
1
Sequential Read
Byte Write
Page Write
1
0
0
≥
1
1
≤
32
RW bit
1
0
1
reSTART, Device Select, RW = 1
As CURRENT or RANDOM Mode
START, Device Select, RW = 0
START, Device Select, RW = 0
Data
Bytes
1
Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
3/18
M34S32
Write Control (WC).
The Write Control feature
WC is useful to protect the contents of the whole
EEPROM area from any erroneous erase/write cy-
cle. It also protects the OTP page against the first
write attempt. The Write Control signal polarity can
be selected with the WCpol bit of the Control Reg-
ister (see Table 13). When pin WC is unconnect-
ed, the WC input is internally read as VIL (see
Table 5).
When WC and WCpol are activating the Write Pro-
tection, Device Select and Address bytes are ac-
knowledged; Data bytes are not acknowledged
(see Figure 11).
Write Control (WCR).
In order to prevent spurious
writes to the Control Register, the user can also
make the Control Register Read Only (Write is in-
hibited). This is achieved by use of the WCR pin
and the CRWD bit (see Table 14) :
– - if CRWD bit = 0, the Control register can be
modified regardless of the state of the WCR pin.
– - if CRWD bit = 1, the Control register can be
modified if the WCR pin is high.
– - if CRWD bit = 1 and the WCR pin is low, the
Control Register is Write Protected.
DEVICE OPERATION
I
2
C Bus Background
The memory supports the extended addressing
I
2
C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver. The de-
vice that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The memory is al-
ways a slave device in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the memory continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to
high transition of the SDA line while the clock SCL
is stable in the high state. A STOP condition termi-
nates communication between the memory and
the bus master. A STOP condition at the end of a
Read command forces the stand-by state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During
the 9th clock pulse the receiver pulls the SDA bus
low to acknowledge the receipt of the 8 bits of da-
ta.
Data Input.
During data input the memory sam-
ples the SDA bus signal on the rising edge of the
clock SCL. For correct device operation the SDA
signal must be stable during the clock low to high
transition and the data must change ONLY when
the SCL line is low.
Device Selection.
To start communication be-
tween the bus master and the slave memory, the
master must initiate a START condition. The 8 bits
sent after a START condition are made up of a De-
vice Select Byte of 4 bits that identifies the device
type, 3 memory block access bits and one bit for a
READ (RW = 1) or WRITE (RW = 0) operation.
There are two modes both for read and write.
These are summarised in Table 4 and described
hereafter. Communication between the master
and the slave is ended with a STOP condition.
Table 5. Input Parameters
(1)
(T
A
= 25°C, f = 400 kHz)
Symbol
C
IN
C
IN
Z
L
Z
H
t
LP
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC, WCR Input Impedance
WC, WCR Input Impedance
Low-pass filter input time constant (SDA and SCL)
V
IN
≤
0.3 V
CC
V
IN
≥
0.7 V
CC
5
500
100
Test Condition
Min.
Max.
8
6
20
Unit
pF
pF
kΩ
kΩ
ns
Note: 1. Sampled only, not 100% tested in production.
4/18
M34S32 -
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I
2
C Bus
VCC
20
Maximum RP value (kΩ)
16
RL
12
8
4
0
10
100
CBUS (pF)
AI01665
RL
SDA
MASTER
fc = 100kHz
fc = 400kHz
SCL
CBUS
CBUS
1000
Table 6. DC Characteristics (T
A
= 0 to 70°C, –40 to 85°C; V
CC
= 4.5V to 5.5V, 2.5V to 5.5V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current (SCL,
SDA)
Output Leakage Current
Supply Current
I
CC
Supply Current (W series)
I
CC1
I
CC2
V
IL
V
IH
V
IL
V
IH
V
OL
Output Low Voltage (W series)
Stand-by Current
Stand-by Current (W series)
Input Low Voltage (WC, WCR)
Input High Voltage (WC, WCR)
Input Low Voltage (other pins)
Input High Voltage (other pins)
Output Low Voltage
I
OL
= 3 mA, V
CC
= 5 V
I
OL
= 2.1 mA, V
CC
= 2.5 V
Test Condition
0
≤
V
IN
≤
V
CC
0
≤
V
OUT
≤
V
CC
; SDA in Hi-Z
V
CC
= 5 V; f
C
= 400 kHz
(rise/fall time < 30 ns)
V
CC
= 2.5 V; f
C
= 400 kHz
(rise/fall time < 30 ns)
V
IN
= V
SS
or V
CC
; V
CC
= 5 V
V
IN
= V
SS
or V
CC
; V
CC
= 2.5 V
– 0.3
V
CC
- 0.5
– 0.3
0.7 V
CC
Min.
Max.
±2
±2
2
1
10
2
0.5
V
CC
+ 1
0.3 V
CC
V
CC
+ 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
V
5/18
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