K4H511638C-ZLB30 datasheet, PDF

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K4H511638C-ZLB30: DescriptionDDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60; Categorystorage storage; File Size393KB，24 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4H511638C-ZLB30 Overview

DDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60

K4H511638C-ZLB30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Humidity sensitivity level	2
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.005 A
Maximum slew rate	0.38 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	10 mm
Base Number Matches	1

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K4H510438C

K4H510838C

K4H511638C

DDR SDRAM

512Mb C-die DDR SDRAM Specification

60 FBGA with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

3. Any system or application incorporating Samsung Memory Product(s) shall be designed to use or access the

memory addresses in a balanced and proportionate manner. Disproportionate, excessive and/or repeated

access to a particular address may result in reduction of product life.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 January 2006

K4H510438C

K4H510838C

K4H511638C

Table of Contents

DDR SDRAM

1.0 Key Features ...............................................................................................................................4

2.0 Ordering Information ...................................................................................................................4

3.0 Operating Frequencies................................................................................................................4

4.0 Pin Description ...........................................................................................................................5

5.0 Package Physical Dimension ....................................................................................................6

6.0 Block Diagram (32Mbit x4 / 16Mbit x8 / 8Mbit x16 I/O x4 Banks).............................................7

7.0 Input/Output Function Description ............................................................................................8

8.0 Command Truth Table.................................................................................................................9

9.0 General Description...................................................................................................................10

10.0 Absolute Maximum Rating .....................................................................................................10

11.0 DC Operating Conditions ........................................................................................................10

12.0 DDR SDRAM IDD Spec Items & Test Conditions ..................................................................11

13.0 Input/Output Capacitance ......................................................................................................11

14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12

15.0 DDR SDRAM IDD spec table ..................................................................................................13

16.0 AC Operating Conditions .......................................................................................................14

17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14

18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15

19.0 AC Timming Parameters & Specifications ...........................................................................16

20.0 System Characteristics for DDR SDRAM ..............................................................................17

21.0 Component Notes ....................................................................................................................18

22.0 System Notes ..........................................................................................................................20

23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21

Rev. 1.3 January 2006

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