Microelectronics
DESCRIPTION
The CE2746 is a mixed signal CMOS monolithic audio
digital to analog converter. It contains six 1-bit sigma delta
DAC. The system consists of 128-time interpolation filters,
4
th
order
Σ∆
modulators, switch capacitors and analog
reconstruction filters. The one bit
Σ∆
converter offers
superior differential linearity, with no distortion due to
component mis-match. high tolerance to clock jitter.
The CE2746 support data conversion from 32K to
192KHz. The analog section operates at 5 volt while the
digital section at 3.3 volt. This dual voltage system reduces
not only the power consumption but also the noise caused
by the digital circuit switching. The CE2746 is ideal for
DVD player, AV receiver and set-top box application.
The CE2746 support 24, 20, 18 and 16-bit input data. It
also support multiple sampling frequency data. Each DAC
has its own individual volume control.
CE2746
6-Channel Audio DAC, 24-bit, 192kHz
FEATURES
• Six Channel Audio DAC.
- 104 dB SNR (A
W
eighted).
- -94 dB THD + N Ratio (A Weighted).
- 8K - 192 KHz. Sampling Rates.
- Independent Digital Volume Control.
- I
2
S, Left and Right Justified Digital Input Formats.
- On -chip Reconstruction Filters.
• 3.3 -volt Digital Interface.
• 2-wire Serial Control Interface.
• 3.3 Volt Digital. 5 Volt Analog Power Supply.
Applications
• Digital Surround Sound For Home Theatre
• DVD
• Car Audio.
XCK
PLL
CE2746
Σ∆
Mod.
D/A
D/A
D/A
D/A
D/A
D/A
AR1
AL1
AR2
AL2
AR3
AL3
DIN1
DIN2
DIN3
80
80
77
INTERPOLATION
DIGITAL
AUDIO
INPUT
FILTER
Σ∆
Mod.
Σ∆
Mod.
LRCK
BCK
77
78
Format
Detect'n
Control
Interface
15
15
SDA
SCL
RST
VCM
CEI Microelectronics Co. Ltd.
1-18
March 24, 2004
CE2746
DAC Performance
Item
1
2
3
4
5
6
7
8
PERFORMANCE SPECIFICATIONS
Audio Output Level
Audio Bandwidth 20Hz - 20 KHz
SNR (A-weight)
THD + NOISE (A-weight, 0 dB input)
Dynamic Range
Channel Separation
Nonlinear Distortion
Channel Gain Error
Spec.
1 Vrms
+/- 0.1 dB
>104 dB
< -88 dB
98 dB
< -90 dB
< 0.25 dB
< 0.1 dB
All Measurement were taken with only one channel active.
2-18
March 24, 2004
CE2746
XCK REQUIREMENT
The CE2746 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for the 96 K
audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
Sampling
Rate
XCK Freq.
CREG1[5:4]=[0 0]
Normal XCK
fs
32 K
44.1
48 K
96 K
192 K
384*fs
12.288 MHz
16.934 Mhz
18.432 MHz
18.432 MHz
18.432 Mhz
256*fs
8.192 MHz
11.29 Mhz.
12.288 Mhz.
12.288 Mhz.
12.288 Mhz.
CREG1[5:4]=[1 0]
4 times XCK
4*384*fs
49.152 MHz
67.738 Mhz
73.728 MHz
73.728 MHz
73.728 Mhz
4*256*fs
32.768 MHz
45.158 Mhz.
49.152 Mhz.
49.152 Mhz.
49.152 Mhz.
CREG1[5:4]=[0 1]
2 times XCK
2*384*fs
24.576 MHz
33.869 Mhz
36.864 MHz
36.864 MHz
36.864 Mhz
2*256*fs
16.384 MHz
22.579 Mhz.
24.576 Mhz.
24.576 Mhz.
24.576 Mhz.
3-18
March 24, 2004
CE2746
PIN ASSIGNMENT
DVDD
XCK
BCK
LRCK
DIN1
DIN2
DIN3
TST
RSTZ
N/C
DGND
TSTOUT
SDA
SCL
1
2
3
4
5
28
27
26
25
24
AVDD
AR1
GR1
AL1
AGND
AR2
GR2
AL2
AGND
AR3
GR3
AL3
VCM
AVDD
CE2746
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
Pin Name
DIGITAL
DVDD
XCK
BCK
LRCk
1
2
3
4
+3.3V
I
I
I
Digital power supply, 3.3 Volt.
External Master Clock Input.
Audio Serial Data Clock Input.
Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in SF
indicates Left Channel Data, a low in SF indicates Right Channel Data. For I2S mode, a
low in SF indicates Left Channel Data, a high in SF indicates Right Channel Data.
Channel 1 Serial Audio Data Input.
Channel 2 Serial Audio Data Input.
Channel 3 Serial Audio Data Input.
Test pin. This pin should be connected to ground.
Active Low Reset Pin.
Open drain output
with a 5 Kohms pull-up resistor. Should leave
open if not connected to system reset.
Not used. can connected to ground.
Pin #
Type
Description
DIN1
DIN2
DIN3
TST
RSTZ
N/C
5
6
7
8
9
10
I
I
I
I
I/O
4-18
March 24, 2004
CE2746
PIN DESCRIPTION (Continued)
Pin Name
DGND
TSTOUT
SDA
Pin #
11
12
13
Type
GND
T
I/O
Digital ground
Tri-state output pin, This pin can be connected to ground or leave open
I2C data bus.
Open drain output.
Externally this pin should tie to a 680 ohm pull up
resistor.
I2C clock input.
Description
SCL
Analog
AVDD
AR1
GR0
AL1
AGND
AR2
GR1
AL2
AGND
AR3
GR2
AL3
VCM
AVDD
14
I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5V
O
GND
O
GND
O
GND
O
GND
O
GND
O
I/O
+5V
Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with
a 0.1 uF.
Analog right channel 1 output
Analog circuits ground
Analog left channel 1 output
Analog circuits ground
Analog right channel 2 output
Analog circuits ground
Analog left channel 2 output
Analog circuits ground
Analog right channel 3 output
Analog circuits ground
Analog right channel 3 output
Common voltage De-coupling Pin Should be Connected to a 22 uF capacitor in parallel
with a 0.1 uF.
Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with
a 0.1 uF.
5-18
March 24, 2004
京公网安备 11010802033920号
EEWORLD
