CM1203
1, 2 and 3-Channel ESD Arrays in CSP
Features
•
•
•
•
•
•
•
•
Functionally and pin compatible with CMD’s
CSPESD301/302/303 family of devices
OptiGuard
™
coated for improved reliability at
assembly
1, 2 or 3 channels of ESD protection
±15kV ESD protection (IEC 61000-4-2, contact
discharge)
±30kV ESD protection (HBM)
Supports both AC and DC signal applications
Low leakage current (<100nA)
Chip Scale Package features extremely low lead
inductance for optimum ESD and filter perfor-
mance
4 bump, 1.06 x 0.93mm footprint Chip Scale Pack-
age (CSP)
Lead-free version available
Product Description
The CM1203 comprises a family of 1, 2, and 3-channel
ESD protection arrays, which integrate two, three and
four identical avalanche-style diodes. It is intended that
one of these diodes is connected to GND and the other
diodes provide ESD protection for up to 3 lines
depending upon the configuration utilized. The back-
to-back diode connections provide ESD protection for
nodes that have AC signals up to 5.9V peak. These
devices provide a very high level of protection for sen-
sitive electronic components that may be subjected to
electrostatic discharge (ESD).
The diodes are
designed and characterized to safely dissipate ESD
strikes of ±15kV, well beyond the maximum require-
ments of the IEC 61000-4-2 international standard.
Using the MIL-STD-883 (Method 3015) specification
for Human Body Model (HBM) ESD, these devices pro-
tect against contact discharges of greater than ±30kV.
The diodes also provide some EMI filtering, when used
in combination with a PCB trace or series resistor.
These devices are particularly well-suited for portable
electronics (e.g. cellular telephones, PDAs, notebook
computers) because of their small package format and
easy-to-use pin assignments.
The CM1203 incorporates OptiGuard
™
coating which
results in improved reliability at assembly. The CM1203
is available in a space-saving, low-profile, chip-scale
package with optional lead-free finishing.
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Applications
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I/O port protection
EMI filtering for data ports
Cellphones, notebook computers, PDAs
Wireless Handsets
MP3 Players
Digital Still Cameras
Handheld PCs
Electrical Schematics
A2
B1
A2
B1
B2
A1
A2
B1
B2
CM1203-01
CM1203-02
CM1203-03
©
2004 California Micro Devices Corp. All rights reserved.
06/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
1
CM1203
PACKAGE / PINOUT DIAGRAMS
TOP VIEW
(Bumps Down View)
Orientation
Marking
(see note 2)
BOTTOM VIEW
(Bumps Up View)
A1
1
A
B
2
A2
A1
B1
n*
B2
Orientation
Marking
* See ordering information for
appropriate part marking.
CM1203
4-Bump CSP Package
Notes:
1) These drawings are not to scale.
2) Lead-free devices are specified by using a "+" character for the top side orientation mark.
3) All 4 bumps are always present. Unused bumps are electrically unconnected.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Bumps
4
4
4
Package
CSP
CSP
CSP
Ordering Part
Number
1
CM1203-01CS
CM1203-02CS
CM1203-03CS
Part Marking
P
Q
R
Lead-free Finish
2
Ordering Part
Number
1
CM1203-01CP
CM1203-02CP
CM1203-03CP
Part Marking
P
Q
R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Note 2: Lead-free devices are specified by using a "
+
" character for the top side orientation mark.
©
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
06/28/04
CM1203
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Storage Temperature Range
DC Package Power Rating
RATING
-65 to +150
200
UNITS
°C
mW
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature Range
RATING
-40 to +85
UNITS
°C
ELECTRICAL OPERATING CHARACTERISTICS
1
SYMBOL
V
SO
I
LEAK
V
SIG
PARAMETER
Diode Stand-off Voltage
Diode Leakage Current
Small Signal Clamp Voltage
Positive Clamp
Negative Clamp
In-system ESD Withstand Voltage
a) Human Body Model, MIL-STD-883,
Method 3015
b) Contact Discharge per IEC 61000-4-2
Clamping Voltage during ESD Discharge
MIL-STD-883 (Method 3015), 8kV
Between adjacent bumps
Between diagonal bumps
Dynamic Resistance
Between adjacent bumps
Between diagonal bumps
Capacitance
CONDITIONS
I
DIODE
=
±10µA
V
IN
=3.3V
I
DIODE
= 10mA
I
DIODE
= -10mA
Notes 2, 3 and 4
±30
±15
Notes 2, 3 and 4
19.5
19.9
Notes 2, 3 and 4
0.85
1.10
At 0VDC, 1MHz, 30mVAC
I
MIN
±5.9
TYP
MAX
UNITS
V
100
6.0
-9.2
7.6
-7.6
9.2
-6.0
nA
V
V
kV
kV
V
ESD
V
CL
V
V
Ω
Ω
pF
R
D
C
27
Note 1: T
A
=25
°
C unless otherwise specified.
Note 2: ESD applied to input and output pins with respect to
another diode, one at a time.
Note 3: Unused pins are left open.
Note 4: These parameters are guaranteed by design and char-
acterization.
I
ESD
slope = 1
/
R
D
10mA
10µA
I
LEAK
3.3V
V
SO
V
SIG
V
CL
V
Figure 1. Parameter Legend
©
2004 California Micro Devices Corp. All rights reserved.
06/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
3
stm32/stm8
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