M28LV64
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
FAST ACCESS TIME: 200ns
SINGLE LOW VOLTAGE OPERATION
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/Busy Open Drain Output
(only on the M28LV64)
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
The M28LV64 is replaced by the
M28C64-xxW
DESCRIPTION
The M28LV64 is an 8K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 2.7V to 3.6V power supply.
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS)
300 mils
TSOP28 (N)
8 x13.4mm
Figure 1. Logic Diagram
VCC
13
A0-A12
8
DQ0-DQ7
Table 1. Signal Names
A0 - A12
DQ0 - DQ7
W
E
G
RB
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Chip Enable
Output Enable
Ready / Busy
Supply Voltage
Ground
W
E
M28LV64
RB *
G
VSS
AI01538B
Note:
* RB function is only available on the M28LV64.
May 1997
This is information on a product still in production bu t not recommended for new de signs.
1/18
M28LV64
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
AI01539B
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
AI01540B
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M28LV64
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
RB
DU
VCC
W
NC
1 32
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
M28LV64
25
17
21
M28LV64
15
14
8
AI01542B
9
Warning:
NC = Not Connected.
Warning:
NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28LV64
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
NC
W
VCC
RB
A12
A7
A6
A5
A4
A3
22
A7
A12
28
1
7
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
AI01541B
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
2/18
M28LV64
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
(1)
Parameter
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
Input/Output Voltage
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Value
– 40 to 85
– 65 to 150
– 0.3 to 6.5
– 0.3 to V
CC
+0.6
– 0.3 to 6.5
4000
Unit
°C
°C
V
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Figure 3. Block Diagram
RB
E
G
W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A12
(Page Address)
ADDRESS
LATCH
64K ARRAY
A0-A5
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI01355
DQ0-DQ7
3/18
M28LV64
Table 3. Operating Modes
Mode
Standby
Output Disable
Write Disable
Read
Write
Note:
1. 0 = V
IL
; 1 = V
IH
; X = V
IL
or V
IH
.
(1)
E
1
X
X
0
0
G
X
1
X
0
1
W
X
X
1
1
0
DQ0 - DQ7
Hi-Z
Hi-Z
Hi-Z
Data Out
Data In
DESCRIPTION
(cont’d)
The M28LV64 outputs the Ready/Busy write
status, the M28LV64-aaaX(aaa = access time) has
no Ready/Busy status and the relevant RB pin is
Not Connected (NC). The circuit has been de-
signed to offer a flexible microcontroller interface
featuring both hardware and software handshak-
ing with Ready/Busy, Data Polling and Toggle Bit.
The M28LV64 supports 64 byte page write opera-
tion. A Software Data Protection (SDP) is also
possible using the standard JEDEC algorithm.
PIN DESCRIPTION
Addresses (A0-A12).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0 - DQ7).
Data is written to or read
from the M28LV64 through the I/O pins.
Write Enable (W).
The Write Enable input controls
the writing of data to the M28LV64.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle (this function applies only to the
M28LV64).
OPERATION
In order to prevent data corruption and inadvertent
writeoperationsan internal V
CC
comparator inhibits
Write operation if V
CC
is below V
WI
(see Table 6).
Access to the memory in write mode is allowed after
a power-up as specified in Table 6.
Read
The M28LV64 is accessed like a static RAM. When
E and G are low with W high, the data addressed
is presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28LV64 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A12 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum data transfer rate of t
WHWH
(see Figure 13).
If a transition of E or W is not detected within t
WHWH
the internal programming cycle will start.
4/18
M28LV64
Microcontroller Control Interface
The M28LV64 provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
be read by asserting Output Enable Low (t
PLTS
).
DQ5 Low indicates the timer is running, High indi-
cates time-out after which the write cycle will start
and no new data may be input.
Re ady/ Busy p in (av ail ab le only on the
M28LV64).
The RB pin provides a signal at its open
drain output which is low during the erase/write
cycle, but which is released at the completionof the
programming cycle.
Software Data Protection
The M28LV64 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28LV64is shipped as standard in the ”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6).
The M28LV64 offers another
way for determining when the internal write cycle
is completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read the memory. When the internal cycle is com-
pleted the toggling will stop and the device will be
accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5).
In the Page
Write mode data may be latched by E or W up to
100µs after the previous byte. Up to 64 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
5/18
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