M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
5V
±10%
SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Stand-by Current: 100µA max
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 07h
DESCRIPTION
The M28F101 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is or-
ganised as 128K bytes of 8 bits. It uses a command
register architecture to select the operating modes
and thus provides a simple microprocessor inter-
face. The M28F101 FLASH Memory is suitable for
applications where the memory has to be repro-
grammed in the equipment. The access time of
70ns makes the device suitable for use in high
speed microprocessor systems.
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC
VPP
17
A0-A16
8
DQ0-DQ7
Table 1. Signal Names
A0-A16
DQ0-DQ7
E
G
W
V
PP
V
CC
V
SS
April 1997
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Write Enable
Program Supply
Supply Voltage
Ground
W
E
G
M28F101
VSS
AI00666B
1/23
M28F101
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
STG
V
IO
V
CC
V
A9
V
PP
Parameter
Ambient Operating Temperature
Storage Temperature
Input or Output Voltages
Supply Voltage
A9 Voltage
Program Supply Voltage, during Erase
or Programming
Value
–40 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
–0.6 to 14
Unit
°C
°C
V
V
V
V
Note:
Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION
The M28F101 FLASH Memory employs a technol-
ogy similar to a 1 Megabit EPROM but adds to the
device functionality by providing electrical erasure
and programming. These functions are managed
by a command register. The functions that are
addressed via the command register depend on
the voltage applied to the V
PP
, program voltage,
input. When V
PP
is less than or equal to 6.5V, the
command register is disabled and M28F101 func-
tions as a read only memory providing operating
modes similar to an EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When V
PP
is raised to 12V the command regsiter
is enabled and this provides, in addition, Erase and
Program operations.
READ ONLY MODES, V
PP
≤
6.5V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
Standby Mode this input is don’t care.
Read Mode.
The M28F101 has two enable inputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independant of the device selection.
Standby Mode.
In the Standby Mode the maxi-
mum supply current is reduced. The device is
placed in the Standby Mode by applying a High to
the Chip Enable (E) input. When in the Standby
Mode the outputs are in a high impedance state,
independant of the Output Enable (G) input.
Output Disable Mode.
When the Output Enable
(G) is High the outputs are in a high impedance
state.
Electronic Signature Mode.
This mode allows the
read out of two binary codes from the device which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automatically select the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
is applied to address line A9 with E and G Low. With
A0 Low the output data is the manufacturer code,
when A0 is High the output is the device type code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
READ/WRITE MODES, 11.4V
≤
V
PP
≤
12.6V
When V
PP
is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute, Erase, Erase Verify, Program, Program Verify
and Reset modes. Each of these modes needs 2
cycles. Eah mode starts with a write operation to
set-up the command, this is followed by either read
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in the memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic Signature Read mode is set-up with one
cycle and followed by a read cycle to output the
manufacturer or device codes.
3/23
M28F101
Table 6. AC Measurement Conditions
SRAM Interface Levels
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
EPROM Interface Levels
≤
10ns
0.45V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01275
1N914
3.3kΩ
EPROM Interface
2.4V
OUT
CL = 30pF or 100pF
0.45V
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
CL includes JIG capacitance
AI01276
Table 7. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% test.ed
READ/WRITE MODES
(cont’d)
A write to the command register is made by bringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage V
CC
and the program voltage
V
PP
can be applied in any order. When the device
is powered up or when V
PP
is
≤
6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addi-
tion a specific command may be used to set the
command register to 00h for reading the memory.
The system designer may chose to provide a con-
stant high V
PP
and use the register commands for
all operations, or to switch the V
PP
from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
V
CC
falls below the Erase/Write Lockout Voltage
(V
LKO
) of 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
5/23
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