M27V405
4 Mbit (512Kb x 8) Low Voltage OTP EPROM
s
LOW VOLTAGE READ OPERATION:
3V to 3.6V
FAST ACCESS TIME: 120ns
LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
s
s
s
s
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIMES:
– Typical 48sec. (PRESTO II Algorithm)
– Typical 27sec. (On-Board Programming)
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
s
PIN COMPATIBLE with the 4 Mbit,
Single Voltage Flash Memory
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B4
Figure 1. Logic Diagram
s
DESCRIPTION
The M27V405 is a low voltage 4 Mbit EPROM of-
fered in the OTP range (one time programmable).
It is ideally suited for microprocessor systems re-
quiring large data or program storage and is orga-
nised as 524,288 by 8 bits.
The M27V405 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
Table 1. Signal Names
A0-A18
Q0-Q7
E
G
V
PP
V
CC
V
SS
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
VCC
VPP
19
A0-A18
8
Q0-Q7
E
G
M27V405
VSS
AI01800
May 1998
1/13
M27V405
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
1 32
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
A9
A11
G
A10
E
Q7
9
M27V405
25
17
Q1
Q2
VSS
Q3
Q4
Q5
Q6
AI01801
A11
A9
A8
A13
A14
A17
VPP
VCC
A18
A16
A15
A12
A7
A6
A5
A4
A12
A15
A16
A18
VCC
VPP
A17
1
32
8
9
M27V405
(Normal)
25
24
16
17
AI01802
G
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qua-
lity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
2/13
M27V405
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
E
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
A9
X
X
X
X
X
X
V
ID
V
PP
V
CC
or V
SS
V
CC
or V
SS
V
PP
V
PP
V
PP
V
CC
or V
SS
V
CC
Q0-Q7
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
1
Q6
0
0
Q5
1
1
Q4
0
1
Q3
0
0
Q2
0
1
Q1
0
0
Q0
0
0
Hex Data
20h
B4h
The M27V405 is pin compatible with the industry
standard 4 Mbit, single voltage Flash Memory. It
can be considered as a Flash Low Cost solution
for production quantities.
The M27V405 can also be operated as a standard
4 Mbit OTP EPROM (similar to M27C405) with a
5V power supply. The M27V405 is offered in
PLCC32 and TSOP32 (12 x 20 mm) packages.
DEVICE OPERATION
The modes of operations of the M27V405 are list-
ed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for V
pp
and 12V on A9 for Elec-
tronic Signature.
Read Mode
The M27V405 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27V405 has a standby mode which reduces
the active current from 15mA to 20µA with low volt-
age operation V
CC
≤
3.6V , see Read Mode DC
Characteristics Table for details. The M27V405 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
3/13
M27V405
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note: Sampled only, not 100% tested.
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS OTP EPROMs require careful decoupling
of the devices. The supply current, I
CC
, has three
segments that are of interest to the system design-
er: the standby current level, the active current lev-
el, and transient current peaks that are produced
4/13
M27V405
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Output High Voltage CMOS
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
I
OH
= –100µA
2.4
V
CC
– 0.7V
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
≤
3.6V
E = V
IH
E > V
CC
– 0.2V, V
CC
≤
3.6V
V
PP
= V
CC
–0.3
2
Min
Max
±10
±10
15
1
20
10
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
M27V405
Symbol
Alt
Parameter
Test Condition
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
E = V
IL
, G = V
IL
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
, G = V
IL
0
0
0
-120
Max
120
120
60
50
50
0
0
0
-150
Min
Max
150
150
80
50
50
ns
ns
ns
ns
ns
ns
Unit
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
by the falling and rising edges of E. The magnitude
of the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/13
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