IS61LPS51218J-166BI datasheet, PDF

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IS61LPS51218J-166BI: DescriptionCache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119; Categorystorage storage; File Size177KB，29 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LPS51218J-166BI Overview

Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119

IS61LPS51218J-166BI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.13 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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IS61LPS25632T/D/J

IS61LPS25636T/D/J

IS61LPS51218T/DJ

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS PIPELINED,

SINGLE-CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE

input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Power Supply

+3.3V Vcc

+3.3V or 2.5 VccQ (I/O)

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• T Versions (three chips selects)

• D Versions (two chips selects)

• J Version (PBGA Pacakge with JTAG)

ISSI

PRELIMINARY INFORMATION

FEBRUARY 2002

DESCRIPTION

The

ISSI

IS61LPS25632T/D/J, IS61LPS25636T/D/J, and

IS61LPS51218T/D/JT/D/JT/D/J are high-speed, low-power

synchronous static RAMs designed to provide burstable, high-

performance memory for communication and networking appli-

cations. The IS61LPS25632T/D/J is organized as 262,144

words by 32 bits and the IS61LPS25636T/D/J is organized

as 262,144 words by 36 bits. The IS61LPS51218T/D/JT/D/

JT/D/J is organized as 524,288 words by 18 bits. Fabricated

with

ISSI

's advanced CMOS technology, the device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to four

bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write enable

(BWE).input combined with one or more individual byte write

signals (BWx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address ad-

vance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

250

-225

2.8

4.4

225

-200

3.1

200

-166

3.5

166

Units

MHz

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00A

02/10/02

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