D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
FSTD32211 40/48-Bit Bus Switch with Level Shifting
September 2001
Revised July 2002
FSTD32211
40/48-Bit Bus Switch with Level Shifting
General Description
The Fairchild Switch FSTD32211 provides up to 48-bits of
high-speed CMOS TTL-compatible bus switching. The low
on resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. A diode to V
CC
has been
integrated into the circuit to allow for level shifting between
5V inputs and 3.3V outputs.
The device can be organized as four 12-bit, two 24-bit, or
one 48-bit bus switch. When routed as a 40-bit bus switch,
the device can be organized as four 10-bit, two 20-bit or
one 40-bit bus switch. When OE
1
is LOW, the switch is ON
and Port 1A is connected to Port 1B. When OE
2
is LOW,
the switch is ON and Port 2A is connected to Port 2B.
When OE
3
is LOW, the switch is ON and Port 3A is con-
nected to Port 3B. When OE
4
is LOW, the switch is ON and
Port 4A is connected to Port 4B. When OE
1
, OE
2
, OE
3
, or
OE
4
are HIGH, a high impedance state exists between the
A and B Ports.
Features
I
4
Ω
switch connection between two ports
I
Voltage level shifting
I
Minimal propagation delay through the switch
I
Low l
CC
I
Zero bounce in flow-through mode
I
Control inputs compatible with TTL level
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
FSTD32211G
(Note 1)(Note 2)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2002 Fairchild Semiconductor Corporation
DS500378
www.fairchildsemi.com
FSTD32211
Connection Diagram
FBGA Pin Assignments
(40-Bit Routing)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1A
2
1A
4
1A
6
1A
8
1A
10
2A
2
2A
4
2A
6
2A
8
2A
10
3A
9
3A
7
3A
5
3A
3
3A
1
4A
9
4A
7
4A
5
4A
3
2
1A
1
1A
3
1A
5
1A
7
1A
9
2A
1
2A
3
2A
5
2A
7
3A
10
3A
8
3A
6
3A
4
3A
2
4A
10
4A
8
4A
6
4A
4
4A
2
3
NC
GND
GND
GND
V
CC
V
CC
V
CC
GND
2A
9
GND
GND
GND
V
CC
V
CC
GND
GND
GND
4A
1
OE
3
4
OE
2
OE
1
GND
GND
V
CC
V
CC
GND
GND
2B
9
GND
GND
V
CC
V
CC
V
CC
GND
GND
4B
1
OE
4
NC
5
1B
1
1B
3
1B
5
1B
7
1B
9
2B
1
2B
3
2B
5
2B
7
3B
10
3B
8
3B
6
3B
4
3B
2
4B
10
4B
8
4B
6
4B
4
4B
2
6
1B
2
1B
4
1B
6
1B
8
1B
10
2B
2
2B
4
2B
6
2B
8
2B
10
3B
9
3B
7
3B
5
3B
3
3B
1
4B
9
4B
7
4B
5
4B
3
(Top Thru View)
W
Pin Descriptions
Pin Name
OE
1
, OE
2
, OE
3
, OE
4
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
Description
Bus Switch Enables
Bus A
Bus B
Truth Tables
Inputs
OE
1
L
L
H
H
Inputs
OE
3
L
L
H
H
OE
4
L
H
L
H
OE
2
L
H
L
H
Inputs/Outputs
1A, 1B
1A
=
1B
1A
=
1B
Z
Z
2A, 2B
2A
=
2B
Z
2A
=
2B
Z
Inputs/Outputs
3A, 3B
3A
=
3B
3A
=
3B
Z
Z
4A, 4B
4A
=
4B
Z
4A
=
4B
Z
www.fairchildsemi.com
2
FSTD32211
Connection Diagram
FBGA Pin Assignments
(48-Bit Routing)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1A
2
1A
4
1A
6
1A
10
1A
12
2A
4
2A
6
2A
8
2A
10
2A
12
3A
11
3A
9
3A
7
3A
5
3A
3
4A
11
4A
9
4A
5
4A
3
2
1A
1
1A
3
1A
5
1A
9
1A
11
2A
3
2A
5
2A
7
2A
9
3A
12
3A
10
3A
8
3A
6
3A
4
4A
12
4A
10
4A
6
4A
4
4A
2
3
NC
1A
7
GND
1A
8
2A
1
2A
2
V
CC
GND
2A
11
GND
GND
GND
3A
2
3A
1
4A
8
4A
7
GND
4A
1
OE
3
4
OE
2
OE
1
1B
7
1B
8
2B
1
2B
2
GND
GND
2B
11
GND
GND
V
CC
3B
2
3B
1
4B
8
4B
7
4B
1
OE
4
NC
5
1B
1
1B
3
1B
5
1B
9
1B
11
2B
3
2B
5
2B
7
2B
9
3B
12
3B
10
3B
8
3B
6
3B
4
4B
12
4B
10
4B
6
4B
4
4B
2
6
1B
2
1B
4
1B
6
1B
10
1B
12
2B
4
2B
6
2B
8
2B
10
2B
12
3B
11
3B
9
3B
7
3B
5
3B
3
4B
11
4B
9
4B
5
4B
3
(Top Thru View)
W
Pin Descriptions
Pin Name
OE
1
, OE
2
, OE
3
, OE
4
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
Description
Bus Switch Enables
Bus A
Bus B
Truth Tables
Inputs
OE
1
L
L
H
H
Inputs
OE
3
L
L
H
H
OE
4
L
H
L
H
OE
2
L
H
L
H
Inputs/Outputs
1A, 1B
1A
=
1B
1A
=
1B
Z
Z
2A, 2B
2A
=
2B
Z
2A
=
2B
Z
Inputs/Outputs
3A, 3B
3A
=
3B
3A
=
3B
Z
Z
4A, 4B
4A
=
4B
Z
4A
=
4B
Z
3
www.fairchildsemi.com
FSTD32211
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
) (Note 4)
DC Input Control Pin Voltage (V
IN
)(Note 5)
DC Input Diode Current (l
IK
) V
IN
<
0V
DC Output (I
OUT
)
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
0.5V to
+
7.0V
Recommended Operating
Conditions
(Note 6)
Power Supply Operating (V
CC)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0 ns/V to 5 ns/V
0 ns/V to DC
-40
°
C to
+
85
°
C
4.5V to 5.5V
0V to 5.5V
0V to 5.5V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
128 mA
+
/
−
100 mA
−
65
°
C to
+
150
°
C
Note 3:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 4:
V
S
is the voltage observed/applied at either A or B Ports across the
switch.
Note 5:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 6:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
I
I
I
OZ
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 8)
I
CC
Quiescent Supply Current
5.5
10
∆
I
CC
Increase in I
CC
per Input
5.5
2.5
µA
mA
V
CC
(V)
4.5
4.5 - 5.5
4.5 - 5.5
4.5 - 5.5
5.5
0
5.5
4.5
4.5
4.5
4
4
35
See Figure 3
±1.0
10
±1.0
7
7
50
1.5
2.0
0.8
T
A
= −40 °C
to
+85 °C
Min
Typ
(Note 7)
Max
−1.2
Units
V
V
V
V
µA
µA
µA
Ω
Ω
Ω
mA
0
≤
V
IN
≤
5.5V
V
IN
=
5.5V
0
≤
A, B
≤
V
CC
V
IN
=
0V, I
IN
=
64 mA
V
IN
=
0V, I
IN
=
30 mA
V
IN
=
2.4V, I
IN
=
15 mA
OE
1
=
OE
2
=
GND
V
IN
=
V
CC
or GND, I
OUT
=
0
OE
1
=
OE
2
=
V
CC
V
IN
=
V
CC
or GND, I
OUT
=
0
One Input at 3.4V
Other Inputs at V
CC
or GND
Note 7:
Typical values are at V
CC
=
5.0V and T
A
= +25°C
Note 8:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
Conditions
I
IN
= −18
mA
www.fairchildsemi.com
4
京公网安备 11010802033920号
EEWORLD
