Data Sheet No. PD60193
IR21093
(S)
HALF-BRIDGE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
•
•
•
•
•
•
•
•
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V, 5V and 15V input logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
High side output in phase with IN input
Logic and power ground +/- 5V offset
Internal 540ns dead-time
Lower di/dt gate driver for better noise immunity
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Dead Time
600V max.
120 mA / 250 mA
10 - 20V
750 & 200 ns
540 ns
Packages
Description
The IR21093(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge-
8-Lead SOIC
8-Lead PDIP
dized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
V
CC
V
CC
IN
V
B
HO
V
S
TO
LOAD
IN
COM
LO
IR21093
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our
Application Notes and DesignTips for proper circuit board layout.
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1
IR21093(
S
)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
S
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 Lead PDIP)
(8 Lead SOIC)
(8 Lead PDIP)
(8 Lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
V
SS
- 0.3
—
—
—
—
—
—
-50
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
Symbol
VB
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
V
SS
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
125
Units
V
°C
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
2
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IR21093(
S
)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF, and T
A
= 25°C, unless otherwise specified.
Symbol
ton
toff
MT
tr
tf
DT
MDT
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
Turn-off fall time
Deadtime: LO turn-off to HO turn-on(DT
LO-HO) &
HO turn-off to LO turn-on (DT
HO-LO)
Deadtime matching = DT
LO - HO
- DT
HO-LO
Min.
—
—
—
—
—
400
—
Typ.
750
200
0
150
50
540
0
Max. Units Test Conditions
950
280
70
220
80
680
60
nsec
V
S
= 0V
V
S
= 0V
V
S
= 0V
V
S
= 0V or 600V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25°C unless otherwise specified. The V
IL
, V
IH
and I
IN
parameters are referenced to COM
and are applicable to the respective input leads. The V
O
, I
O
and Ron parameters are referenced to COM and are applicable to
the respective output leads: HO and LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Definition
Logic “1” input voltage for HO & logic “0” for LO
Logic “0” input voltage for HO & logic “1” for LO
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
and V
BS
supply undervoltage positive going
threshold
V
CC
and V
BS
supply undervoltage negative going
threshold
Hysteresis
Output high short circuit pulsed vurrent
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.9
—
—
—
—
20
0.4
—
—
8.0
7.4
0.3
120
250
—
—
0.8
0.3
—
60
1.0
5
1
8.9
8.2
0.7
200
350
—
0.8
1.4
0.6
50
150
1.6
20
2
9.8
9.0
—
—
—
V
O
= 0V, PW
≤
10 µs
V
O
= 15V,PW
≤
10 µs
µA
mA
V
V
CC
= 10V to 20V
V
CC
= 10V to 20V
I
O
= 20 mA
I
O
= 20 mA
V
B
= V
S
= 600V
V
IN
= 0V or 5V
V
IN
= 0V or 5V
RDT = 0
µA
IN = 5V, SD = 0V
IN = 0V, SD = 5V
V
mA
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3
IR21093(
S
)
Functional Block Diagrams
VB
IR21093
IN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
VS
DEADTIME
UV
DETECT
VCC
LO
VSS/COM
LEVEL
SHIFT
DELAY
COM
Lead Definitions
Symbol Description
IN
V
B
HO
V
S
V
CC
LO
COM
Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM)
High side floating supply
High side gate drive output
High side floating supply return
Low side and logic fixed supply
Low side gate drive output
Low side return
4
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IR21093(
S
)
Lead Assignments
1
2
3
4
VCC
IN
COM
LO
VB
HO
VS
8
7
6
5
1
2
3
4
VCC
IN
COM
LO
VB
HO
VS
8
7
6
5
8-Lead PDIP
8-Lead SOIC
IR21093
IR21093S
IN
(LO)
IN
50%
50%
IN
(HO)
ton
HO
tr
90%
toff
90%
tf
LO
LO
HO
Figure 1. Input/Output Timing Diagram
10%
10%
Figure 2. Switching Time Waveform Definitions
IN
(LO)
50%
50%
50%
50%
IN
IN
(HO)
90%
LO
HO
10%
HO
DT
10%
DT
LO
MT
90%
MT
90%
10%
LO
Figure 3. Deadtime Waveform Definitions
HO
Figure 4. Delay Matching Waveform Definitions
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