CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUB-
GROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
2.2
-
2.6
-
-10
-10
3.0
-
-
MAX
-
0.8
-
0.4
+10
+10
-
0.8
500
UNITS
V
V
V
V
µA
µA
V
V
µA
PARAMETER
Logical One Input
Voltage
Logical Zero Input
Voltage
Output HlGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Clock lnput High
Clock Input Low
Standby Power Supply
Current
Operating Power
Supply Current
Functional Test
SYMBOL
V
lH
V
IL
V
OH
V
OL
I
I
I
O
TEST CONDITIONS
V
DD
= 5.5V
V
DD
= 4.5V
I
OH
= -400µA
V
DD
= 4.5V (Note 2)
I
OL = +2.0mA
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND
V
CC
= 5.5V
V
OUT
= V
CC
or GND
V
CC
= 5.5V
V
CC
= 5.5V
V
CC
= 4.5V
V
IN
= V
CC
or GND
V
CC
= 5.5V,
Outputs Open
f = 33MHz
V
CC
= 5.5V (Note 3)
(Note 4)
V
IHC
V
ILC
I
CCSB
I
CCOP
1, 2, 3
7, 8
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
-
99
-
mA
FT
NOTES:
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 3mA/MHz.
4. Tested as follows: t = 1MHz, V
IH
= 2.6, V
IL
= 0.4, V
OH
≥
1.5V, V
OL
<
1.5V, V
IHC
= 3.4V, and V
ILC
= 0.4V.
9-17
HSP45240/883
TABLE 2. AC ELECTRICAL SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUP
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9,10,11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
(
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-25 (25MHz)
MIN
39
15
15
17
0
5
0
18
18
39
15
0
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
18
18
-33 (33MHz)
MIN
30
12
12
16
0
5
0
14
14
30
12
0
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
16
16
-40 (40MHz)
MIN
25
10
10
14
0
5
0
12
12
25
10
0
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
14
14
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
Clock Period
Clock Pulse Width High
Clock Pulse Width Low
Setup Time D0-6 to WR
High
Hold Time D0-6 from WR
Low
Setup Time A, CS to WR
Low
Hold Time A, CS from
WR High
Pulse Width for WR Low
Pulse Width for WR High
WR Cycle Time
Set-up Time STARTIN,
DLYBLK, to Clock High
Hold Time STARTlN,
DLYBLK, to Clock High
Clock to Output Prop.
Delay on OUT0-23
Clock to Prop. Delay, on
STARTOUT, BLKDONE,
DONE, ADVAL, and
BUSY
Output Enable Time
(Note 6)
RST Low Time
NOTES:
SYMBOL
t
CP
t
CH
t
CL
t
DS
t
DH
t
AS
t
AH
t
WRL
t
WRH
t
WP
t
IS
t
lH
t
PDO
t
PDS
t
EN
t
RST
9, 10, 11
9, 10, 11
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
22
-
20
-
15
ns
ns
2 Clock Cycles
5. AC Testing: V
CC
= 4.5V and 5.5V, inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements
are made at 1.5V for both a logic “1” and “‘0”. CLK is driven at 4.0V and 0V and measured at 2.0V.
6. Transition is measured at
±200mV
from steady state voltage with loading as specified by test load circuit and C
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