The ACTQ574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs
OE
DS100243-3
Internal
D
L
H
L
H
L
H
L
H
Q
NC
NC
L
H
L
H
NC
NC
Outputs
O
N
Z
Z
Z
Z
L
H
NC
NC
Hold
Hold
Function
CP
H
H
N
N
N
N
H
H
H
H
L
L
L
L
Pin Assignment for LCC
Load
Load
Data Available
Data Available
No Change in
Data
No Change in
Data
H
H
DS100243-4
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
DS100243-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
Junction Temperature (T
J
)
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACTQ
Minimum Input Edge Rate
∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
±
50 mA
±
50 mA
−65˚C to +150˚C
125 mV/ns
Note 1:
All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
™
circuits outside databook specifications.
±
300 mA
DC Electrical Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
(Note 3)
V
IN
= V
IL
or V
IH
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
(Note 3)
V
IN
= V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND (Note 5)
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
Units
Conditions
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
V
V
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input Leakage Current
Maximum TRI-STATE
Leakage Current
Maximum I
CC
/Input
(Note 4)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
0.50
0.50
V
µA
µA
mA
mA
mA
µA
±
1.0
±
5.0
1.6
50
−50
80.0
3
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DC Electrical Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
V
OLP
V
OLV
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
CC
for 54ACTQ
@
25˚C is identical to 74ACTQ
@
25˚C.
Note 6:
Plastic DIP package.
Note 7:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
@
GND.
(Continued)
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
1.5
−1.2
Units
Conditions
5.0
5.0
V
V
(Notes 6, 7)
(Notes 6, 7)
Note 8:
Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 9)
Min
f
max
t
PLH
,
t
PHL
t
PZH
,
t
PZL
t
PHZ
,
t
PLZ
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 10:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
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