Philips Semiconductors
Product data sheet
2-to-1 I
2
C master selector with interrupt logic and reset
PCA9541
DESCRIPTION
The PCA9541 is a 2-to-1 I
2
C master selector designed for high
reliability dual master I
2
C applications where system operation is
required, even when one master fails or the controller card is
removed for maintenance. The two masters (e.g., primary and
back-up) are located on separate I
2
C-buses that connect to the
same downstream I
2
C-bus slave devices. I
2
C commands are sent
by either I
2
C-bus master and are used to select one master at a
time. Either master at any time can gain control of the slave devices
if the other master is disabled or removed from the system. The
failed master is isolated from the system and will not affect
communication between the on-line master and the slave devices on
the downstream I
2
C-bus.
Three versions are offered for different architectures. PCA9541/01
with channel 0 selected at start-up, PCA9541/02 with channel 0
selected after start-up and after stop condition is detected, and
PCA9541/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which
master has control of the bus. One interrupt input (INT_IN) collects
downstream information and propagates it to the 2 upstream
I
2
C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used
to let the previous bus master know that it is not in control of the bus
anymore and to indicate the completion of the bus
recovery/initialization sequence. Those interrupts can be disabled
and will not generate an interrupt if the masking option is set.
A bus recovery/initialization if enabled sends nine clock pulses, a
not acknowledge, and a stop condition in order to set the
downstream I
2
C-bus devices to an initialized state before actually
switching the channel to the selected master.
An interrupt is sent to the upstream channel when the
recovery/initialization procedure is completed.
An internal bus sensor senses the downstream I
2
C traffic and
generates an interrupt if a channel switch occurs during a non-idle
bus condition. This function is enabled when the PCA9541
recovery/initialization is not used. The interrupt signal informs the
master that an external I
2
C-bus recovery/initialization needs to be
performed. It can be disabled and an interrupt will not be generated.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage, which will be
passed by the PCA9541. This allows the use of different bus
voltages on each pair, so that 1.8 V 2.5 V or 3.3 V devices can
communicate with 5 V devices without any additional protection.
The PCA9541 does not isolate the capacitive loading on either side
of the device so the designer must take into account all trace and
device capacitances on both sides of the device, and pull-up
resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for
each channel. All I/O pins are 6.0 V tolerant.
An active-LOW Reset Input allows the PCA9541 to be initialized.
Pulling the RESET pin LOW resets the I
2
C state machine and
configures the device to its default state as does the internal power
on reset function.
FEATURES
•
2-to-1 bi-directional master selector
•
I
2
C interface logic; compatible with SMBus standards
•
PCA9541/01 powers-up with Channel 0 selected
•
PCA9541/02 powers-up with Channel 0 selected after STOP
•
PCA9541/03 powers-up with no channel selected and either
•
Active LOW Interrupt Input
•
2 Active LOW Interrupt Outputs
•
Active LOW Reset Input
•
4 address pins allowing up to 16 devices on the I
2
C-bus
•
Channel selection via I
2
C-bus
•
Bus initialization/recovery function
•
Bus traffic sensor
•
Low Rds
ON
switches
•
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
•
No glitch on power-up
•
Supports hot insertion
•
Software identical for both masters
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
6.0 V tolerant Inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Packages offered: SO16, TSSOP16, HVQFN16
APPLICATIONS
exceeds 100 mA
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
5 V buses
master can take control of the bus
condition detected (bus idle) on Channel 0
•
High reliability systems with dual masters
•
Gatekeeper multiplexer on long single bus
•
Bus initialization/recovery for slave devices without hardware
•
Allows masters without arbitration logic to share resources
reset
2004 Oct 01
2
Philips Semiconductors
Product data sheet
2-to-1 I
2
C master selector with interrupt logic and reset
PCA9541
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic TSSOP
16-Pin Plastic HVQFN
16-Pin Plastic SO
16-Pin Plastic TSSOP
16-Pin Plastic HVQFN
16-Pin Plastic SO
16-Pin Plastic TSSOP
16-Pin Plastic HVQFN
TEMPERATURE RANGE
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
ORDER CODE
PCA9541D/01
PCA9541PW/01
PCA9541BS/01
PCA9541D/02
PCA9541PW/02
PCA9541BS/02
PCA9541D/03
PCA9541PW/03
PCA9541BS/03
TOPSIDE MARK
PCA9541D/01
9541/01
41/1
PCA9541D/02
9541/02
41/2
PCA9541D/03
9541/03
41/3
DRAWING NUMBER
SOT109-1
SOT403-1
SOT629-1
SOT109-1
SOT403-1
SOT629-1
SOT109-1
SOT403-1
SOT629-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16 V
DD
15 INT_IN
14 SDA_SLAVE
13 SCL_SLAVE
12 A3
11 A2
10 A1
9
A0
RESET 2
SCL_MST1 3
SDA_MST1 4
6
7
5
8
11 SCL_SLAVE
SCL_MST0 1
16 SDA_MST0
SDA_MST0
SCL_MST0
RESET
SCL_MST1
SDA_MST1
INT1
V
SS
13 INT_IN
12 SDA_SLAVE
10 A3
9
A2
A1
INT0
15 INT0
V
SS
TOP VIEW
SW02008
Figure 1. SO16/TSSOP16 pin configuration.
SW02034
Figure 2. HVQFN16 pin configuration.
PIN DESCRIPTION
SO/TSSOP
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVQFN PIN NUMBER
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
INT0
SDA_MST0
SCL_MST0
RESET
SCL_MST1
SDA_MST1
INT1
V
SS
A0
A1
A2
A3
SCL_SLAVE
SDA_SLAVE
INT_IN
V
DD
FUNCTION
Active LOW interrupt output 0 (external pull-up required)
Serial data master 0 (external pull-up required)
Serial clock master 0 (external pull-up required)
Active LOW reset input (external pull-up required)
Serial clock master 1 (external pull-up required)
Serial data master 1 (external pull-up required)
Active LOW interrupt output 1 (external pull-up required)
Supply ground
Address input 0 (externally held to GND or V
CC
)
Address input 1 (externally held to GND or V
CC
)
Address input 2 (externally held to GND or V
CC
)
Address input 3 (externally held to GND or V
CC
)
Serial clock slave (external pull-up required)
Serial data slave (external pull-up required)
Active LOW interrupt input (external pull-up required)
Supply voltage
2004 Oct 01
3
INT1
A0
14 V
DD
Philips Semiconductors
Product data sheet
2-to-1 I
2
C master selector with interrupt logic and reset
PCA9541
DEVICE ADDRESS
Following a START condition, the upstream master that wants to
control the I
2
C-bus or make a status check must send the address
of the slave it is accessing. The slave address of the PCA9541 is
shown in Figure 4. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable pins and they must be
pulled HIGH or LOW.
The 2 LSBS are used as a pointer to determine which register will
be accessed.
If the auto-increment flag is set (AI=1), the two least significant bits
of the Command Code are automatically incremented after a byte
has been read or written. This allows the user to program the
registers sequentially or to read them sequentially.
–
During a Read operation, the contents of these bits will rollover
to “00” after the last allowed register is accessed (“10”).
–
During a Write operation, the PCA9541 will acknowledge bytes
sent to the IE and CONTROL registers but will not acknowledge
a byte sent to the Interrupt Status Register since it is a
read-only register. The 2 LSB’s of the Command Code do not
roll over to 00 but stays at 10.
1
1
1
A3 A2
A1 A0 R/W
FIXED
HARDWARE
SELECTABLE
SW02011
Only the 2 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes. Any command code
(Write operation) different from “000AI0000”, “000AI0001”, and
“000AI0010” will not be acknowledged. At power-up, this register
defaults to all zeros.
Figure 4. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1 a read is selected while logic 0
selects a write operation.
COMMAND CODE
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9541, which will be stored
in the Command Code register.
Table 1. Command Code Register
B1
0
B0
0
1
0
1
REGISTER
NAME
IE
CONTROL
ISTAT
TYPE
Read/Write
Read/Write
Read
NOT ALLOWED
REGISTER
FUNCTION
Interrupt
Enable
Control Switch
Interrupt
Status
0
0
0
AI
0
0
B1 B0
0
1
AUTO
INCREMENT
REGISTER
NUMBER
1
SW02302
Figure 5. Command Code
Each system master controls its own set of registers, however they
can also read specific bits from the other system master.
PCA9541 INTERNAL REGISTER MAP
IE
CONTROL
ISTAT
REG#00
REG#01
REG#10
IE
CONTROL
ISTAT
IE 0
CONTROL 0
ISTAT 0
IE 1
CONTROL 1
ISTAT 1
REG#00
REG#01
REG#10
MASTER 0
SCL_MST0
SDA_MST0
CONTROL 0
PCA9541
MASTER 1
SCL_MST1
SDA_MST1
CONTROL 1
7
6
5
4
3
2
1
0
SW02072
CONTROL REGISTER DETAIL
Figure 6. Internal register map
2004 Oct 01
5
Embedded System
京公网安备 11010802033920号
EEWORLD
