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IS61WV25616BLL-10BI-TR

Description
Standard SRAM, 256KX16, 10ns, CMOS, PBGA48
Categorystorage    storage   
File Size422KB,22 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
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IS61WV25616BLL-10BI-TR Overview

Standard SRAM, 256KX16, 10ns, CMOS, PBGA48

IS61WV25616BLL-10BI-TR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
package instructionFBGA, BGA48,6X8,30
Reach Compliance Codecompliant
Factory Lead Time8 weeks
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PBGA-B48
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of terminals48
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA48,6X8,30
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Parallel/SerialPARALLEL
power supply2.5/3.3 V
Certification statusNot Qualified
Maximum standby current0.009 A
Minimum standby current2 V
Maximum slew rate0.045 mA
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
Base Number Matches1
IS61WV25616ALL/ALS
IS61WV25616BLL/BLS
IS64WV25616BLL/BLS
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
FEBRUARY 2017
FEATURES
HIGH SPEED: (IS61/64WV25616ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
LOW POWER: (IS61/64WV25616ALS/BLS)
• High-speed access time: 25, 35, 45 ns
• Low Active Power: 35 mW (typical)
• Low Standby Power: 0.6 mW (typical)
CMOS standby
• Single power supply
— V
dd
1.65V to 2.2V (IS61WV25616Axx)
— V
dd
2.4V to 3.6V (IS61/64WV25616Bxx)
Fully static operation: no clock or refresh required
Three state outputs
Data control for upper and lower bytes
Industrial and Automotive temperature support
Lead-free available
are high-speed, 4,194,304-bit static RAMs organized as
262,144 words by 16 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV25616Axx/Bxx and IS64WV25616Bxx are
packaged in the JEDEC standard 44-pin 400mil SOJ,
44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
DESCRIPTION
The
ISSI
IS61WV25616Axx/Bxx and IS64WV25616Bxx
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H1
02/10/2017
1

IS61WV25616BLL-10BI-TR Related Products

IS61WV25616BLL-10BI-TR IS64WV25616BLL-10CTLA3 IS64WV25616BLL-10BLA3-TR
Description Standard SRAM, 256KX16, 10ns, CMOS, PBGA48 Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, TSOP2-44 Standard SRAM, 256KX16, 10ns, CMOS, PBGA48
Is it Rohs certified? incompatible conform to conform to
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Reach Compliance Code compliant compliant compliant
Factory Lead Time 8 weeks 12 weeks 12 weeks
Maximum access time 10 ns 10 ns 10 ns
I/O type COMMON COMMON COMMON
JESD-30 code R-PBGA-B48 R-PDSO-G44 R-PBGA-B48
memory density 4194304 bit 4194304 bit 4194304 bit
Memory IC Type STANDARD SRAM STANDARD SRAM STANDARD SRAM
memory width 16 16 16
Number of terminals 48 44 48
word count 262144 words 262144 words 262144 words
character code 256000 256000 256000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 85 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
organize 256KX16 256KX16 256KX16
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FBGA TSOP2 FBGA
Encapsulate equivalent code BGA48,6X8,30 TSOP44,.46,32 BGA48,6X8,30
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, FINE PITCH SMALL OUTLINE, THIN PROFILE GRID ARRAY, FINE PITCH
Parallel/Serial PARALLEL PARALLEL PARALLEL
power supply 2.5/3.3 V 2.5/3.3 V 2.5/3.3 V
Certification status Not Qualified Not Qualified Not Qualified
Maximum standby current 0.009 A 0.015 A 0.015 A
Minimum standby current 2 V 2 V 2 V
Maximum slew rate 0.045 mA 0.065 mA 0.065 mA
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL AUTOMOTIVE AUTOMOTIVE
Terminal form BALL GULL WING BALL
Terminal pitch 0.75 mm 0.8 mm 0.75 mm
Terminal location BOTTOM DUAL BOTTOM
package instruction FBGA, BGA48,6X8,30 TSOP2, TSOP44,.46,32 -
Base Number Matches 1 1 -
Filter level - AEC-Q100 AEC-Q100
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