5962-8873303ZC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 5962-8873303ZC

5962-8873303ZC: DescriptionMultiplier Accumulator/Summer, 16-Bit, CMOS, CPGA68, CAVITY-DOWN, CERAMIC, PGA-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size246KB，7 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

Download Datasheet Parametric Compare View All

5962-8873303ZC Overview

Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA68, CAVITY-DOWN, CERAMIC, PGA-68

5962-8873303ZC Parametric

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	PGA,
Contacts	68
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ
boundary scan	NO
External data bus width	16
JESD-30 code	S-CPGA-P68
JESD-609 code	e4
length	29.4386 mm
low power mode	NO
Number of terminals	68
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output data bus width	35
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.81 mm
Maximum slew rate	25 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	29.4386 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER
Base Number Matches	1

Preview

Download Datasheet

View All

5962-8873303ZC Related Products

	5962-8873303ZC	5962-8873301XC	5962-8873302ZC	5962-8873303XC	5962-8873302UC	5962-8873302YC	5962-8873301YC	5962-8873302XC	5962-8873303YC
Description	Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA68, CAVITY-DOWN, CERAMIC, PGA-68	Multiplier Accumulator/Summer, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY DOWN, HERMETIC SEALED, SIDE BRAZED, DIP-64	Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA68, CAVITY-DOWN, CERAMIC, PGA-68	Multiplier Accumulator/Summer, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY DOWN, HERMETIC SEALED, SIDE BRAZED, DIP-64	Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA68, CAVITY-DOWN, CERAMIC, PGA-68	Multiplier Accumulator/Summer, 16-Bit, CMOS, CQCC68, 0.950 X 0.950 INCH, CERAMIC, LCC-68	Multiplier Accumulator/Summer, 16-Bit, CMOS, CQCC68, 0.950 X 0.950 INCH, CERAMIC, LCC-68	Multiplier Accumulator/Summer, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY DOWN, HERMETIC SEALED, SIDE BRAZED, DIP-64	Multiplier Accumulator/Summer, 16-Bit, CMOS, CQCC68, 0.950 X 0.950 INCH, CERAMIC, LCC-68
Parts packaging code	PGA	DIP	PGA	DIP	PGA	LCC	LCC	DIP	LCC
package instruction	PGA,	DIP, DIP64,.9	PGA,	DIP, DIP64,.9	PGA, PGA68,11X11	QCCN, LCC68,.95SQ	QCCN, LCC68,.95SQ	DIP, DIP64,.9	QCCN, LCC68,.95SQ
Contacts	68	64	68	64	68	68	68	64	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 5MHZ
boundary scan	NO	NO	NO	NO	NO	NO	NO	NO	NO
External data bus width	16	16	16	16	16	16	16	16	16
JESD-30 code	S-CPGA-P68	R-CDIP-T64	S-CPGA-P68	R-CDIP-T64	S-CPGA-P68	S-CQCC-N68	S-CQCC-N68	R-CDIP-T64	S-CQCC-N68
JESD-609 code	e4	e4	e4	e4	e4	e4	e4	e4	e4
length	29.4386 mm	81.28 mm	29.4386 mm	81.28 mm	29.4386 mm	24.1935 mm	24.1935 mm	81.28 mm	24.1935 mm
low power mode	NO	NO	NO	NO	NO	NO	NO	NO	NO
Number of terminals	68	64	68	64	68	68	68	64	68
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Output data bus width	35	35	35	35	35	35	35	35	35
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	DIP	PGA	DIP	PGA	QCCN	QCCN	DIP	QCCN
Package shape	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	SQUARE	SQUARE	RECTANGULAR	SQUARE
Package form	GRID ARRAY	IN-LINE	GRID ARRAY	IN-LINE	GRID ARRAY	CHIP CARRIER	CHIP CARRIER	IN-LINE	CHIP CARRIER
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.81 mm	3.81 mm	3.81 mm	3.81 mm	3.81 mm	3.048 mm	3.048 mm	3.81 mm	3.048 mm
Maximum slew rate	25 mA	25 mA	25 mA	25 mA	25 mA	25 mA	25 mA	25 mA	25 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	YES	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	GOLD	GOLD	GOLD	GOLD	Gold (Au)	Gold (Au)	GOLD	Gold (Au)	Gold (Au)
Terminal form	PIN/PEG	THROUGH-HOLE	PIN/PEG	THROUGH-HOLE	PIN/PEG	NO LEAD	NO LEAD	THROUGH-HOLE	NO LEAD
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm
Terminal location	PERPENDICULAR	DUAL	PERPENDICULAR	DUAL	PERPENDICULAR	QUAD	QUAD	DUAL	QUAD
width	29.4386 mm	22.86 mm	29.4386 mm	22.86 mm	29.4386 mm	24.1935 mm	24.1935 mm	22.86 mm	24.1935 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER
Base Number Matches	1	1	1	1	1	1	1	1	1
Is it Rohs certified?	-	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Humidity sensitivity level	-	3	-	3	3	3	3	3	3
Encapsulate equivalent code	-	DIP64,.9	-	DIP64,.9	PGA68,11X11	LCC68,.95SQ	LCC68,.95SQ	DIP64,.9	LCC68,.95SQ
power supply	-	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V
Filter level	-	38535Q/M;38534H;883B	-	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535Q/M;38534H;883B

Recommended Resources

Liquid level indication circuit design based on LM1830

Pressure automatic control circuit

60 seconds display circuit

Fast acting signal generation circuit with various waveforms

Circuit diagram of using large capacitor C to replace backup battery

AM receiving circuit using integrated circuit TDAl072A

Have you ever made a managed switch?: What chip is used in the switch? Please recommend and have complete information...; youmuren NXP MCU

Unboxing experience~~FPGA (cyclone4) development board: The board has arrived. It's better than expected, and the black color looks very high-end....; MQ_H FPGA/CPLD

DAC80508 Multi-channel DAC Application in High-precision Test Measurement: In the development and application of test and measurement equipment, how to achieve the compensation of signal chain DC Offset and how to obtain high-precision flexible and adjustable voltage output ...; alan000345 Microcontroller MCU

Questions about the SPI module of G2553: New students have questions: Previously, SPI and IIC protocols were all handled by software to simulate IO ports. Now that the MSP430 hardware integrates these modules, does it mean that SPI can be us...; 595818431 TI Technology Forum

Current flow in three-phase full-bridge inverter topology: [Ask if you don't understand] In the figure, if the drive signals of T1, T3, and T5 (the three upper tubes) are all low, and the currents of phases A and C are positive, and the potential of phase B i...; shaorc Power technology

TIVA C Launchpad Week 1: [b]德州电影 (TI) LaunchPad 展开官方资料[/b][b]入门[font=Tahoma, Helvetica, SimSun, sans-serif][size=14px][url=http://www.ti.com /ww/cn/launchpad/home_head.html]http://www.ti.com/ww/cn/launchpad/home_head.html[/ur...; dzc2001 Microcontroller MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components