BUS-65112-140S datasheet, PDF - EEWORLD Datasheet

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BUS-65112-140S: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, HERMETIC SEALED, DDIP-78; CategoryThe embedded processor and controller Microcontrollers and processors; File Size70KB，4 Pages; ManufacturerData Device Corporation

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BUS-65112-140S Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, HERMETIC SEALED, DDIP-78

BUS-65112-140S Parametric

Parameter Name	Attribute value
Maker	Data Device Corporation
Parts packaging code	QIP
package instruction	QIP,
Contacts	78
Reach Compliance Code	unknown
Address bus width	12
boundary scan	NO
maximum clock frequency	12 MHz
letter of agreement	MIL-STD-1553
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-XQIP-P78
low power mode	NO
Number of serial I/Os	2
Number of terminals	78
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	QIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Maximum seat height	5.334 mm
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	QUAD
width	41.91 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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BUS-65112 and BUS-65117

MIL-STD-1553 DUAL REDUNDANT

REMOTE TERMINAL HYBRID

FEATURES

BUS-65112 DDIP

BUS-65117 Flat Pack

•

Small Size and Low Power

•

Complete RTU Protocol

•

Supports 13 Mode Codes:

Any Combination Can be Illegalized

DESCRIPTION

The BUS-65112 is a complete dual

redundant MIL-STD-1553 Remote

Terminal Unit (RTU) packaged in a

small 1.9” x 2.1” hybrid. Based upon

DDC custom ICs, it includes two

transceivers, two encoder/decoders,

two bit processors, RTU protocol,

data buffers, and timing control

logic. It supports all 13 mode codes

for dual redundant operation, any

combination of which can be illegal-

ized.

Parallel data transfers are accom-

plished with a DMA-type hand-

shaking, compatible with most CPU

types. Data transfers to/from memo-

ry are simplified by the latched com-

mand word and word count out-

puts. Error detection and recovery

are enhanced by BUS-65112 spe-

cial features. A 14-bit built-in-test

word register stores RTU informa-

tion, and sends it to the Bus

Controller in response to the Mode

Command Transmit Bit Word. The

BUS-65112 performs continuous

on-line wraparound self-test, and

provides four error flags to the host

CPU. Inputs are provided for host

CPU control of six bits of the RTU

Status Word.

Its small hermetic package, -55°C to

+125°C operating temperature

range, and complete RTU operation

make the BUS-65112 ideal for most

MIL-STD-1553 applications.

•

Transfers Data with DMA-Type

Handshaking

•

Latched Outputs for Command Word

and Word Count

•

14-Bit Built-in-Test Word Register

•

Four Error Flag Outputs

•

Continuous Online Self-Test

•

Plug-in and Flat Pack Packaging

DATA

BUS A

TRANSCEIVER

ENCODER/

DECODER

BIT

PROCESSOR

BUFFER

DB0-DB15

BUF ENA

DTREQ

DTGRT

DTACK

DTSTB

R/W

TRANSFER

CONTROLS

DATA

BUS B

TRANSCEIVER

ENCODER/

DECODER

BIT

PROCESSOR

CURRENT

WORD

COUNTER

MUX

PROTOCOL

SEQUENCER

AND

CONTROL

LOGIC

COMMAND

LATCH

A0-A4

A6-A11

DAT/CMD

ILL CMD (ME)

SS REQ

ADBC

RT FLAG

SS BUSY

SS FLAG

MESS ERR

RT FAIL

HS FAIL

RTADD ERR

NBGT

INCMD

BITEN

STATEN

GBR

STATUS

ERROR FLAGS

TIMING FLAGS

BU-65112/655117 BLOCK DIAGRAM

1995, 1999 Data Device Corporation

Custom DDC Monolithics utilized in this product are copyright under the Semiconductor Chip Protection Act.

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