HUF75309P3, HUF75309D3, HUF75309D3S
Data Sheet
December 2001
19A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75309.
Features
• 19A, 55V
• Simulation Models
- Temperature Compensated PSPICE
®
and SABER
™
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
HUF75309P3
HUF75309D3
HUF75309D3S
PACKAGE
TO-220AB
TO-251AA
TO-252AA
BRAND
75309P
75309D
75309D
S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF75309D3ST.
Packaging
JEDEC STYLE TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
JEDEC TO-251AA
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B
HUF75309P3, HUF75309D3, HUF75309D3S
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
55
55
±20
19
Figure 4
Figures 6, 14, 15
55
0.37
-55 to 175
300
260
UNITS
V
V
V
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 50V, V
GS
= 0V
V
DS
= 45V, V
GS
= 0V, T
C
= 150
o
C
V
GS
=
±20V
55
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
I
GSS
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 19A, V
GS
= 10V (Figure 9)
2
-
-
0 .060
4
0.070
V
Ω
R
θJC
R
θJA
(Figure 3)
TO-220
TO-251, TO-252
-
-
-
-
-
-
2.7
62
100
o
C/W
o
C/W
o
C/W
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Reverse Transfer Capacitance
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 30V,
I
D
≅
19A,
R
L
= 1.58Ω
I
g(REF)
= 1.0mA
(Figure13)
-
-
-
-
-
20
11
0.68
1.8
5
24
13.5
0.85
-
-
nC
nC
nC
nC
nC
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 30V, I
D
≅
19A,
R
L
= 1.58Ω, V
GS
=
10V,
R
GS
= 27Ω
-
-
-
-
-
-
-
7
39
24
30
-
70
-
-
-
-
80
ns
ns
ns
ns
ns
ns
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B
HUF75309P3, HUF75309D3, HUF75309D3S
Electrical Specifications
PARAMETER
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
350
150
39
-
-
-
pF
pF
pF
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 19A
I
SD
= 19A, dI
SD
/dt = 100A/µs
I
SD
= 19A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
-
MAX
1.25
50
70
UNITS
V
ns
nC
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
20
I
D
, DRAIN CURRENT (A)
2
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
15
10
5
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
SINGLE PULSE
0.01
10
-5
10
-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B
HUF75309P3, HUF75309D3, HUF75309D3S
Typical Performance Curves
500
(Continued)
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
175 - T
C
150
100
V
GS
= 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
100
I
AS
, AVALANCHE CURRENT (A)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
SINGLE PULSE
T
C
= 25
o
C
200
100
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
100µs
10
STARTING T
J
= 25
o
C
10
STARTING T
J
= 150
o
C
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
V
DSS(MAX)
= 55V
1
1
10
1ms
10ms
100
200
1
0.001
0.01
0.1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
40
V
GS
= 20V
I
D
, DRAIN CURRENT (A)
32
V
GS
= 10V
V
GS
= 7V
I
D
, DRAIN CURRENT (A)
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
32
25
o
C
24
175
o
C
-55
o
C
24
V
GS
= 6V
16
V
GS
= 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX, T
C
= 25
o
C
0
2
4
6
8
16
8
8
V
DD
= 15V
0
0
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B
HUF75309P3, HUF75309D3, HUF75309D3S
Typical Performance Curves
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs, V
GS
= 10V, I
D
= 19A
DUTY CYCLE = 0.5% MAX
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
(Continued)
1.2
V
GS
= V
DS
, I
D
= 250µA
1.0
1.5
0.8
1.0
0.5
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
0.6
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
C, CAPACITANCE (pF)
500
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
400
C
ISS
300
1.1
1.0
200
C
OSS
100
C
RSS
0.9
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
0
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 30V
8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
6
4
2
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 19A
I
D
= 15A
I
D
= 10A
I
D
= 5A
0
3
6
Q
g
, GATE CHARGE (nC)
9
12
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B
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