EEWORLDEEWORLDEEWORLD

Part Number

Search

DM74AS244WMX

Description
Bus Driver, AS Series, 2-Func, 4-Bit, True Output, TTL, PDSO20, 0.300 INCH, SOIC-20
Categorylogic    logic   
File Size56KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric View All

DM74AS244WMX Online Shopping

Suppliers Part Number Price MOQ In stock  
DM74AS244WMX - - View Buy Now

DM74AS244WMX Overview

Bus Driver, AS Series, 2-Func, 4-Bit, True Output, TTL, PDSO20, 0.300 INCH, SOIC-20

DM74AS244WMX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction0.300 INCH, SOIC-20
Contacts20
Reach Compliance Codeunknown
Control typeENABLE LOW
seriesAS
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.8 mm
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.064 A
Humidity sensitivity level1
Number of digits4
Number of functions2
Number of ports2
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)90 mA
Prop。Delay @ Nom-Sup6.2 ns
propagation delay (tpd)6.2 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm
Base Number Matches1
DM74AS240 • DM74AS244 3-STATE Bus Driver/Receiver
October 1986
Revised March 2000
DM74AS240 • DM74AS244
3-STATE Bus Driver/Receiver
General Description
This family of Advance Schottky 3-STATE Bus circuits are
designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communi-
cation Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated trans-
mission lines down to 133Ω. The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package con-
tains eight 3-STATE buffers organized with four buffers
having a common 3-STATE enable gate. The DM74AS240
and DM74AS244 are eight wide in a 20 pin package, and
may be used as a 4 wide bidirectional or eight wide unidi-
rectional. The buffer selection includes inverting and non-
inverting, with enable or disable 3-STATE control.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Improved switching performance with less power dissi-
pation compared with Schottky counterpart
s
Functional and pin compatible with 74LS and Schottky
counterpart
s
Switching response specified into 500Ω and 50 pF
s
Specified to interface with CMOS at V
OH
=
V
CC
2V
Ordering Code:
Order Number
DM74AS240WM
DM74AS240N
DM74AS244WM
DM74AS244N
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74AS240
DM74AS244
Function Tables
DM74AS240
Inputs
G
L
L
H
A
L
H
X
Output
Y
H
L
Z
H
=
HIGH Logic Level
DM74AS244
Inputs
G
L
L
H
X
=
Either LOW or HIGH Logic Level
Output
A
L
H
X
Y
L
H
Z
L
=
LOW Logic Level
Z
=
High Impedance
© 2000 Fairchild Semiconductor Corporation
DS006298
www.fairchildsemi.com
Please advise on the LCD of STM8S105S4
I need his information urgently, thank you very much...
wang1jin stm32/stm8
Why is the 430 adc initialization reset statement written twice?
void ADC_init(void) { ADC12CTL0=0; ADC12CTL0=0; ADC12CTL1=0; ADC12IE =0; ADC12IFG= 0; } This is an ADC initialization program written by a senior. I saw that in many places in his program, the command...
天天1 Microcontroller MCU
The best Linux distributions of 2011
Here is a list of the top seven Linux operating systems for 2011.  Ubuntu is an operating system built by a global team of professional developers. It includes all the applications you need: browser, ...
wanghongyang Talking
Briefly describe chip packaging technology
(I) Since Intel Corporation of the United States designed and manufactured a 4-bit microprocessor chip in 1971, in more than 20 years, CPUs have evolved from Intel 4004, 80286, 80386, ......
zzzzer16 PCB Design
Design and analysis of dual battery power supply scheme based on bq24161+TPS2419
Welcome to download and share...
德州仪器 Analogue and Mixed Signal
A novice asks a question about the simulation process
[backcolor=white]I would like to ask, No Nios II target connection paths were located. Check connections and that a Nios II .sof is download. After clicking refresh, there is still no response. What's...
不是归人是过客 FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 601  2833  2203  279  2486  13  58  45  6  51 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号