Femtoclocks® Crystal-to-3.3V
LVPECL Frequency Synthesizer
843004-01
Data Sheet
G
ENERAL
D
ESCRIPTION
The 843004-01 is a 4 output LVPECL synthesizer optimized to
generate Ethernet reference clock frequencies and is a member
of the family of high performance clock solutions from IDT. Using
a 25MHz 18pF parallel resonant crystal, the following frequencies
can be generated based on the settings of 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. The 843004-01
uses IDT’s 3
rd
generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 843004-01 is packaged in a small
24-pin TSSOP package.
F
EATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase noise at 156.25MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ................-95.5 dBc/Hz
1kHz .................-118 dBc/Hz
10kHz .................-126 dBc/Hz
100kHz ..............-126.6 dBc/Hz
• Full 3.3V supply mode
• -30°C to 85°C ambient operating temperature
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Divider
Value
25
25
25
25
N Divider
Value
4
5
10
not used
M/N
Divider Value
6.25
5
2.5
• Available in lead-free RoHS compliant package
Output Frequency
(25MHz Ref.)
156.25
125
62.5
not used
P
IN
A
SSIGNMENT
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
V
CC
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
2
843004-01
F_SEL[1:0]
Q0
nQO
Q1
nQ1
TEST_CLK
Pulldown
25MHz
1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1
not used
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
0
Q2
nQ2
M = 25 (fixed)
Q3
nQ3
MR
Pulldown
©2016 Integrated Device Technology, Inc
1
Revision B
January 18, 2016
843004-01 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
CCO
Q0, nQ0
MR
Power
Ouput
Input
Type
Output
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When LOW,
Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Negative supply pins.
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
7
8
9
10, 12
11, 18
13, 14
15, 19
16
17
20, 21
23, 24
Pulldown
nPLL_SEL
nc
V
CCA
F_SEL0,
F_SEL1
V
CC
XTAL_OUT,
XTAL_IN
V
EE
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
©2016 Integrated Device Technology, Inc
2
Revision B
January 18, 2016
843004-01 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
135
15
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
nPLL_SEL, nXTAL_SEL,
Input
F_SEL0, F_SEL1, MR
Low Voltage
TEST_CLK
TEST_CLK, MR, nPLL_
Input
SEL, nXTAL_SEL, F_SEL0,
High Current
F_SEL1
TEST_CLK, MR, nPLL_
Input
SEL, nXTAL_SEL, F_SEL0,
Low Current
F_SEL1
Test Conditions
Minimum
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
Typical
Maximum
V
CC
+ 0.3
0.8
1.3
150
Units
V
V
V
µA
I
IH
I
IL
V
CC
= 3.465V, V
IN
= 0V
-5
µA
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Ω
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
- 2V.
©2016 Integrated Device Technology, Inc
3
Revision B
January 18, 2016
843004-01 Data Sheet
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical Maximum
25
50
7
Units
MHz
Ω
pF
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz (1.875MHz - 20MHz)
RMS Phase Jitter; NOTE 3
Output Rise/Fall Time
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
300
0.57
0.63
0.81
600
51
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] =10
Minimum
140
112
56
Typical
Maximum
170
136
68
30
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CCO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Phase jitter is dependent on the input source used.
©2016 Integrated Device Technology, Inc
4
Revision B
January 18, 2016
843004-01 Data Sheet
0
-10
-20
-30
-40
-50
T
YPICAL
P
HASE
N
OISE AT
62.5MH
Z
➤
10Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.81ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-180
-190 100
1k
10k
-170
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
-10
-20
-30
-40
-50
➤
0
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
10Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.63ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
Raw Phase Noise Data
➤
O
FFSET
F
REQUENCY
(H
Z
)
©2016 Integrated Device Technology, Inc
➤
➤
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100k
1M
10M
100M
➤
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100k
1M
10M
100M
5
Revision B
January 18, 2016
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